Date: Tue, 11 Apr 2006 19:42:32 GMT From: Warner Losh <imp@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 95015 for review Message-ID: <200604111942.k3BJgWuP008765@repoman.freebsd.org>
next in thread | raw e-mail | index | archive | help
http://perforce.freebsd.org/chv.cgi?CH=95015 Change 95015 by imp@imp_hammer on 2006/04/11 19:41:31 Better parameters Affected files ... .. //depot/projects/arm/src/sys/boot/arm/kb920x/boot0/at91rm9200_lowlevel.c#11 edit .. //depot/projects/arm/src/sys/boot/arm/kb920x/boot0/at91rm9200_lowlevel.h#5 edit Differences ... ==== //depot/projects/arm/src/sys/boot/arm/kb920x/boot0/at91rm9200_lowlevel.c#11 (text+ko) ==== @@ -42,7 +42,7 @@ register unsigned value; int i; - volatile unsigned short *p = (unsigned short *)SDRAM_BASE; + volatile sdram_size_t *p = (sdram_size_t *)SDRAM_BASE; AT91C_BASE_PIOC->PIO_PER = AT91C_PIO_PC10; AT91C_BASE_PIOC->PIO_OER = AT91C_PIO_PC10; @@ -105,16 +105,16 @@ AT91C_BASE_EBI->EBI_CSA = value; AT91C_BASE_SDRC->SDRC_CR = - AT91C_SDRC_NC_9 | - AT91C_SDRC_NR_13 | - AT91C_SDRC_NB_4_BANKS | - AT91C_SDRC_CAS_2 | - ((2 << 7) & AT91C_SDRC_TWR) | - ((5 << 11) & AT91C_SDRC_TRC) | - ((2 << 15) & AT91C_SDRC_TRP) | - ((2 << 19) & AT91C_SDRC_TRCD) | - ((4 << 23) & AT91C_SDRC_TRAS) | - ((6 << 27) & AT91C_SDRC_TXSR); + AT91C_SDRC_NC_9 | + AT91C_SDRC_NR_13 | + AT91C_SDRC_NB_4_BANKS | + AT91C_SDRC_CAS_2 | + ((2 << 7) & AT91C_SDRC_TWR) | + ((5 << 11) & AT91C_SDRC_TRC) | + ((2 << 15) & AT91C_SDRC_TRP) | + ((2 << 19) & AT91C_SDRC_TRCD) | + ((4 << 23) & AT91C_SDRC_TRAS) | + ((6 << 27) & AT91C_SDRC_TXSR); AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_PRCGALL_CMD; ==== //depot/projects/arm/src/sys/boot/arm/kb920x/boot0/at91rm9200_lowlevel.h#5 (text+ko) ==== @@ -33,16 +33,18 @@ /* The following divisor sets PLLA frequency: e.g. 10/5 * 90 = 180MHz */ #define OSC_MAIN_FREQ_DIV 5 /* for 10MHz osc */ #define SDRAM_WIDTH AT91C_SDRC_DBW_16_BITS +typedef unsigned short sdram_size_t; +#define OSC_MAIN_MULT 90 #endif #ifdef BOOT0_TSC -/* The following divisor sets PLLA frequency: e.g. 16/8 * 90 = 180MHz */ -#define OSC_MAIN_FREQ_DIV 8 /* for 16MHz osc */ +/* The following divisor sets PLLA frequency: e.g. 16/4 * 45 = 180MHz */ +#define OSC_MAIN_FREQ_DIV 4 /* for 16MHz osc */ #define SDRAM_WIDTH AT91C_SDRC_DBW_32_BITS +typedef unsigned int sdram_size_t; +#define OSC_MAIN_MULT 45 #endif -#define OSC_MAIN_MULT 90 /* Constant for both */ - /* Master clock frequency at power-up */ #define AT91C_MASTER_CLOCK 60000000
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?200604111942.k3BJgWuP008765>