Date: Wed, 18 Mar 2009 20:35:48 GMT From: Ulf Lilleengen <lulf@FreeBSD.org> To: Perforce Change Reviews <perforce@FreeBSD.org> Subject: PERFORCE change 159402 for review Message-ID: <200903182035.n2IKZmsm013197@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=159402 Change 159402 by lulf@lulf_carrot on 2009/03/18 20:35:04 - Change the set_rate and get_rate interface a bit to operate on the clocks themselves. Implement the set_rate and get_rate for the current clocks, and use this in atmel_mci. Affected files ... .. //depot/projects/avr32/src/sys/avr32/avr32/at32.c#9 edit .. //depot/projects/avr32/src/sys/avr32/avr32/at32_pm.c#5 edit .. //depot/projects/avr32/src/sys/dev/mmc/atmel_mci.c#2 edit .. //depot/projects/avr32/src/sys/kern/devclk_if.m#4 edit .. //depot/projects/avr32/src/sys/kern/subr_devclk.c#4 edit .. //depot/projects/avr32/src/sys/sys/devclk.h#4 edit Differences ... ==== //depot/projects/avr32/src/sys/avr32/avr32/at32.c#9 (text+ko) ==== ==== //depot/projects/avr32/src/sys/avr32/avr32/at32_pm.c#5 (text+ko) ==== @@ -67,10 +67,18 @@ static void at32_pbb_enable(devclk_t, int); static void at32_pbb_disable(devclk_t, int); +static uint64_t at32_pbb_get_rate(devclk_t, int); +static int at32_pbb_set_rate(devclk_t, int, uint64_t); + static void at32_pll_enable(devclk_t, int); static void at32_pll_disable(devclk_t, int); +static uint64_t at32_pll_get_rate(devclk_t, int); +static int at32_pll_set_rate(devclk_t, int, uint64_t); + static void at32_osc_enable(devclk_t, int); static void at32_osc_disable(devclk_t, int); +static uint64_t at32_osc_get_rate(devclk_t, int); +static int at32_osc_set_rate(devclk_t, int, uint64_t); /* Driver variables and private data */ struct at32_pm_softc { @@ -101,8 +109,8 @@ static kobj_method_t at32_osc_methods[] = { KOBJMETHOD(devclk_enable, at32_osc_enable), KOBJMETHOD(devclk_disable, at32_osc_disable), -/* KOBJMETHOD(devclk_set_rate, at32_osc_set_rate), - KOBJMETHOD(devclk_get_rate, at32_osc_get_rate),*/ + KOBJMETHOD(devclk_set_rate, at32_osc_set_rate), + KOBJMETHOD(devclk_get_rate, at32_osc_get_rate), {0, 0}, }; DEFINE_CLASS(at32_osc, at32_osc_methods, sizeof(struct devclk)); @@ -111,8 +119,8 @@ static kobj_method_t at32_pll_methods[] = { KOBJMETHOD(devclk_enable, at32_pll_enable), KOBJMETHOD(devclk_disable, at32_pll_disable), -/* KOBJMETHOD(devclk_set_rate, at32_pll_set_rate), - KOBJMETHOD(devclk_get_rate, at32_pll_get_rate),*/ + KOBJMETHOD(devclk_set_rate, at32_pll_set_rate), + KOBJMETHOD(devclk_get_rate, at32_pll_get_rate), {0, 0}, }; DEFINE_CLASS(at32_pll, at32_pll_methods, sizeof(struct devclk)); @@ -121,8 +129,8 @@ static kobj_method_t at32_pbb_methods[] = { KOBJMETHOD(devclk_enable, at32_pbb_enable), KOBJMETHOD(devclk_disable, at32_pbb_disable), -/* KOBJMETHOD(devclk_set_rate, at32_pbb_set_rate), - KOBJMETHOD(devclk_get_rate, at32_pbb_get_rate),*/ + KOBJMETHOD(devclk_set_rate, at32_pbb_set_rate), + KOBJMETHOD(devclk_get_rate, at32_pbb_get_rate), {0, 0}, }; DEFINE_CLASS(at32_pbb, at32_pbb_methods, sizeof(struct devclk)); @@ -237,6 +245,21 @@ WR4(AT32_PM_PBBMASK, reg & ~(1 << index)); } +extern uint64_t clock_cpu_frequency; + +static uint64_t +at32_pbb_get_rate(devclk_t clk, int index) +{ + /* XXX: Temporary. */ + return (clock_cpu_frequency); +} + +static int +at32_pbb_set_rate(devclk_t clk, int index, uint64_t rate) +{ + return (0); +} + static void at32_osc_enable(devclk_t clk, int index) { @@ -265,6 +288,35 @@ } } +static uint64_t +at32_osc_get_rate(devclk_t clk, int index) +{ + /* In this case, index means which oscilliator. */ + switch (index) { + case 0: /* OSC0 */ + break; + case 1: /* OSC1 */ + break; + case 2: /* OSC32 */ + break; + } +} + +static int +at32_osc_set_rate(devclk_t clk, int index, uint64_t rate) +{ + /* In this case, index means which oscilliator. */ + switch (index) { + case 0: /* OSC0 */ + break; + case 1: /* OSC1 */ + break; + case 2: /* OSC32 */ + break; + } + return (0); +} + static void at32_pll_enable(devclk_t clk, int index) { @@ -288,3 +340,27 @@ break; } } + +static uint64_t +at32_pll_get_rate(devclk_t clk, int index) +{ + switch (index) { + case 0: /* PLL0 */ + break; + case 1: /* PLL1 */ + break; + } + return (0); +} + +static int +at32_pll_set_rate(devclk_t clk, int index, uint64_t rate) +{ + switch (index) { + case 0: /* PLL0 */ + break; + case 1: /* PLL1 */ + break; + } + return (0); +} ==== //depot/projects/avr32/src/sys/dev/mmc/atmel_mci.c#2 (text+ko) ==== @@ -31,6 +31,7 @@ #include <sys/systm.h> #include <sys/bio.h> #include <sys/bus.h> +#include <sys/devclk.h> #include <sys/conf.h> #include <sys/endian.h> #include <sys/kernel.h> @@ -65,7 +66,7 @@ #define BBSZ 512 /* XXX: Temporary. */ -extern uint64_t clock_cpu_frequency; +static uint64_t mci_clockfreq; struct atmel_mci_softc { void *intrhand; /* Interrupt handle */ @@ -200,8 +201,9 @@ atmel_MCI_LOCK_DESTROY(sc); goto out; } + mci_clockfreq = devclk_get_rate(dev); sc->host.f_min = 375000; //XXX - sc->host.f_max = clock_cpu_frequency / 2; /* Typically 65 MHz (XXX: too much?) */ + sc->host.f_max = mci_clockfreq / 2; /* Typically 65 MHz (XXX: too much?) */ sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; if (sc->wire4) sc->host.caps = MMC_CAP_4_BIT_DATA; @@ -230,6 +232,9 @@ struct atmel_mci_softc *sc; int rid; + /* Enable device clock before writing. */ + devclk_enable(dev); + sc = device_get_softc(dev); rid = 0; sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, @@ -265,6 +270,9 @@ bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), sc->irq_res); sc->irq_res = 0; + + /* Turn off device clock. */ + devclk_disable(dev); return; } @@ -292,10 +300,10 @@ clkdiv = 0; } else { WR4(sc, MCI_CR, MCI_CR_MCIEN); - if ((clock_cpu_frequency % (ios->clock * 2)) == 0) - clkdiv = ((clock_cpu_frequency / ios->clock) / 2) - 1; + if ((mci_clockfreq % (ios->clock * 2)) == 0) + clkdiv = ((mci_clockfreq / ios->clock) / 2) - 1; else - clkdiv = (clock_cpu_frequency / ios->clock) / 2; + clkdiv = (mci_clockfreq / ios->clock) / 2; } if (ios->bus_width == bus_width_4) WR4(sc, MCI_SDCR, RD4(sc, MCI_SDCR) | MCI_SDCR_SDCBUS); @@ -339,10 +347,10 @@ if (!data) { // The no data case is fairly simple atmel_mci_pdc_disable(sc); -// printf("CMDR %x ARGR %x\n", cmdr, cmd->arg); + printf("CMDR %x ARGR %x\n", cmdr, cmd->arg); WR4(sc, MCI_ARGR, cmd->arg); WR4(sc, MCI_CMDR, cmdr); - WR4(sc, MCI_IER, MCI_SR_ERROR | MCI_SR_CMDRDY); + WR4(sc, MCI_IER, 0xffffffff); //MCI_SR_ERROR | MCI_SR_CMDRDY); return; } if (data->flags & MMC_DATA_READ) ==== //depot/projects/avr32/src/sys/kern/devclk_if.m#4 (text+ko) ==== @@ -32,14 +32,14 @@ # Get device clock rate METHOD uint64_t get_rate { - device_t _dev; - device_t _child; + devclk_t _clk; + int _index; }; # Set device clock rate METHOD int set_rate { - device_t _dev; - device_t _child; + devclk_t _clk; + int _index; uint64_t _rate; }; ==== //depot/projects/avr32/src/sys/kern/subr_devclk.c#4 (text+ko) ==== @@ -65,24 +65,36 @@ uint64_t devclk_get_rate(device_t dev) { -#if 0 - device_t parent = device_get_parent(dev); - if (parent) { - return (DEVCLK_GET_RATE(parent, dev)); + struct devclk_map *map; + devclk_t clk; + /* XXX: We need to think of the mapping here. */ + STAILQ_FOREACH(map, &devclk_maps, link) { + if (map->dev != dev) + continue; + clk = devclk_find_clock(map->clk_name); + if (clk == NULL) + continue; + return (DEVCLK_GET_RATE(clk, map->clk_index)); } -#endif - return (0); + return (EINVAL); } int devclk_set_rate(device_t dev, uint64_t rate) { -#if 0 - device_t parent = device_get_parent(dev); - if (parent) { - return (DEVCLK_SET_RATE(parent, dev, rate)); + struct devclk_map *map; + devclk_t clk; + /* XXX: We need to think of the mapping here. */ + STAILQ_FOREACH(map, &devclk_maps, link) { + if (map->dev != dev) + continue; + clk = devclk_find_clock(map->clk_name); + if (clk == NULL) + continue; + /* XXX: Enable parent too ? */ + DEVCLK_SET_RATE(clk, map->clk_index, rate); + return (0); } -#endif return (EINVAL); } ==== //depot/projects/avr32/src/sys/sys/devclk.h#4 (text+ko) ====
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