Date: Wed, 14 Jul 2010 00:41:23 +0000 (UTC) From: Warner Losh <imp@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r210038 - head/sys/mips/mips Message-ID: <201007140041.o6E0fNwY003856@svn.freebsd.org>
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Author: imp Date: Wed Jul 14 00:41:22 2010 New Revision: 210038 URL: http://svn.freebsd.org/changeset/base/210038 Log: Prefer the cpuregs.h spellings of register and bit names over cpu.h. Modified: head/sys/mips/mips/exception.S head/sys/mips/mips/fp.S head/sys/mips/mips/machdep.c head/sys/mips/mips/mpboot.S head/sys/mips/mips/pm_machdep.c head/sys/mips/mips/psraccess.S head/sys/mips/mips/support.S head/sys/mips/mips/swtch.S head/sys/mips/mips/trap.c head/sys/mips/mips/vm_machdep.c Modified: head/sys/mips/mips/exception.S ============================================================================== --- head/sys/mips/mips/exception.S Tue Jul 13 23:58:10 2010 (r210037) +++ head/sys/mips/mips/exception.S Wed Jul 14 00:41:22 2010 (r210038) @@ -115,7 +115,7 @@ VECTOR(MipsTLBMiss, unknown) .set push .set noat j MipsDoTLBMiss - MFC0 k0, COP_0_BAD_VADDR # get the fault address + MFC0 k0, MIPS_COP_0_BAD_VADDR # get the fault address .set pop VECTOR_END(MipsTLBMiss) @@ -144,7 +144,7 @@ MipsDoTLBMiss: PTR_ADDU k1, k0, k1 #07: k1=seg entry address PTR_L k1, 0(k1) #08: k1=seg entry - MFC0 k0, COP_0_BAD_VADDR #09: k0=bad address (again) + MFC0 k0, MIPS_COP_0_BAD_VADDR #09: k0=bad address (again) beq k1, zero, 2f #0a: ==0 -- no page table srl k0, PAGE_SHIFT - 2 #0b: k0=VPN (aka va>>10) andi k0, k0, 0xff8 #0c: k0=page tab offset @@ -152,10 +152,10 @@ MipsDoTLBMiss: lw k0, 0(k1) #0e: k0=lo0 pte lw k1, 4(k1) #0f: k1=lo0 pte CLEAR_PTE_SWBITS(k0) - MTC0 k0, COP_0_TLB_LO0 #12: lo0 is loaded + MTC0 k0, MIPS_COP_0_TLB_LO0 #12: lo0 is loaded COP0_SYNC CLEAR_PTE_SWBITS(k1) - MTC0 k1, COP_0_TLB_LO1 #15: lo1 is loaded + MTC0 k1, MIPS_COP_0_TLB_LO1 #15: lo1 is loaded COP0_SYNC tlbwr #1a: write to tlb HAZARD_DELAY @@ -176,13 +176,13 @@ VECTOR(MipsException, unknown) * Find out what mode we came from and jump to the proper handler. */ .set noat - mfc0 k0, COP_0_STATUS_REG # Get the status register - mfc0 k1, COP_0_CAUSE_REG # Get the cause register value. + mfc0 k0, MIPS_COP_0_STATUS # Get the status register + mfc0 k1, MIPS_COP_0_CAUSE # Get the cause register value. and k0, k0, SR_KSU_USER # test for user mode # sneaky but the bits are # with us........ sll k0, k0, 3 # shift user bit for cause index - and k1, k1, CR_EXC_CODE # Mask out the cause bits. + and k1, k1, MIPS3_CR_EXC_CODE # Mask out the cause bits. or k1, k1, k0 # change index to user table #if defined(__mips_n64) PTR_SLL k1, k1, 1 # shift to get 8-byte offset @@ -207,7 +207,7 @@ VECTOR_END(MipsException) */ SlowFault: .set noat - mfc0 k0, COP_0_STATUS_REG + mfc0 k0, MIPS_COP_0_STATUS nop and k0, k0, SR_KSU_USER bne k0, zero, _C_LABEL(MipsUserGenException) @@ -237,28 +237,28 @@ SlowFault: #if defined(TARGET_OCTEON) #define CLEAR_STATUS \ - mfc0 a0, COP_0_STATUS_REG ;\ + mfc0 a0, MIPS_COP_0_STATUS ;\ li a2, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) ; \ or a0, a0, a2 ; \ li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | SR_KSU_USER) ; \ and a0, a0, a2 ; \ - mtc0 a0, COP_0_STATUS_REG ; \ + mtc0 a0, MIPS_COP_0_STATUS ; \ ITLBNOPFIX #elif defined(TARGET_XLR_XLS) #define CLEAR_STATUS \ - mfc0 a0, COP_0_STATUS_REG ;\ + mfc0 a0, MIPS_COP_0_STATUS ;\ li a2, (MIPS_SR_KX | MIPS_SR_COP_2_BIT) ; \ or a0, a0, a2 ; \ li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | SR_KSU_USER) ; \ and a0, a0, a2 ; \ - mtc0 a0, COP_0_STATUS_REG ; \ + mtc0 a0, MIPS_COP_0_STATUS ; \ ITLBNOPFIX #else #define CLEAR_STATUS \ - mfc0 a0, COP_0_STATUS_REG ;\ + mfc0 a0, MIPS_COP_0_STATUS ;\ li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | SR_KSU_USER) ; \ and a0, a0, a2 ; \ - mtc0 a0, COP_0_STATUS_REG ; \ + mtc0 a0, MIPS_COP_0_STATUS ; \ ITLBNOPFIX #endif @@ -302,10 +302,10 @@ SlowFault: SAVE_REG(s8, S8, sp) ;\ mflo v0 ;\ mfhi v1 ;\ - mfc0 a0, COP_0_STATUS_REG ;\ - mfc0 a1, COP_0_CAUSE_REG ;\ - MFC0 a2, COP_0_BAD_VADDR ;\ - MFC0 a3, COP_0_EXC_PC ;\ + mfc0 a0, MIPS_COP_0_STATUS ;\ + mfc0 a1, MIPS_COP_0_CAUSE ;\ + MFC0 a2, MIPS_COP_0_BAD_VADDR;\ + MFC0 a3, MIPS_COP_0_EXC_PC ;\ SAVE_REG(v0, MULLO, sp) ;\ SAVE_REG(v1, MULHI, sp) ;\ SAVE_REG(a0, SR, sp) ;\ @@ -332,7 +332,7 @@ SlowFault: RESTORE_REG(t1, MULHI, sp) ;\ mtlo t0 ;\ mthi t1 ;\ - MTC0 v0, COP_0_EXC_PC ;\ + MTC0 v0, MIPS_COP_0_EXC_PC ;\ .set noat ;\ RESTORE_REG(AT, AST, sp) ;\ RESTORE_REG(v0, V0, sp) ;\ @@ -363,7 +363,7 @@ SlowFault: RESTORE_REG(gp, GP, sp) ;\ RESTORE_REG(ra, RA, sp) ;\ PTR_ADDU sp, sp, KERN_EXC_FRAME_SIZE;\ - mtc0 k0, COP_0_STATUS_REG + mtc0 k0, MIPS_COP_0_STATUS /* @@ -396,10 +396,10 @@ NNON_LEAF(MipsKernGenException, KERN_EXC * intr filters if interrupts are enabled later * in trap handler */ - mfc0 a0, COP_0_STATUS_REG - and a0, a0, SR_INT_MASK + mfc0 a0, MIPS_COP_0_STATUS + and a0, a0, MIPS_SR_INT_MASK RESTORE_REG(a1, SR, sp) - and a1, a1, ~SR_INT_MASK + and a1, a1, ~MIPS_SR_INT_MASK or a1, a1, a0 SAVE_REG(a1, SR, sp) RESTORE_CPU # v0 contains the return address. @@ -452,22 +452,22 @@ NNON_LEAF(MipsUserGenException, CALLFRAM SAVE_U_PCB_REG(t2, T2, k1) SAVE_U_PCB_REG(t3, T3, k1) SAVE_U_PCB_REG(ta0, TA0, k1) - mfc0 a0, COP_0_STATUS_REG # First arg is the status reg. + mfc0 a0, MIPS_COP_0_STATUS # First arg is the status reg. SAVE_U_PCB_REG(ta1, TA1, k1) SAVE_U_PCB_REG(ta2, TA2, k1) SAVE_U_PCB_REG(ta3, TA3, k1) SAVE_U_PCB_REG(s0, S0, k1) - mfc0 a1, COP_0_CAUSE_REG # Second arg is the cause reg. + mfc0 a1, MIPS_COP_0_CAUSE # Second arg is the cause reg. SAVE_U_PCB_REG(s1, S1, k1) SAVE_U_PCB_REG(s2, S2, k1) SAVE_U_PCB_REG(s3, S3, k1) SAVE_U_PCB_REG(s4, S4, k1) - MFC0 a2, COP_0_BAD_VADDR # Third arg is the fault addr + MFC0 a2, MIPS_COP_0_BAD_VADDR # Third arg is the fault addr SAVE_U_PCB_REG(s5, S5, k1) SAVE_U_PCB_REG(s6, S6, k1) SAVE_U_PCB_REG(s7, S7, k1) SAVE_U_PCB_REG(t8, T8, k1) - MFC0 a3, COP_0_EXC_PC # Fourth arg is the pc. + MFC0 a3, MIPS_COP_0_EXC_PC # Fourth arg is the pc. SAVE_U_PCB_REG(t9, T9, k1) SAVE_U_PCB_REG(gp, GP, k1) SAVE_U_PCB_REG(sp, SP, k1) @@ -483,13 +483,13 @@ NNON_LEAF(MipsUserGenException, CALLFRAM REG_S a3, CALLFRAME_RA(sp) # for debugging PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP # Turn off fpu and enter kernel mode - and t0, a0, ~(SR_COP_1_BIT | SR_EXL | SR_KSU_MASK | SR_INT_ENAB) + and t0, a0, ~(MIPS_SR_COP_1_BIT | MIPS_SR_EXL | MIPS3_SR_KSU_MASK | MIPS_SR_INT_IE) #if defined(TARGET_OCTEON) - or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS32_SR_PX) + or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS_SR_PX) #elif defined(TARGET_XLR_XLS) or t0, t0, (MIPS_SR_KX | MIPS_SR_COP_2_BIT) #endif - mtc0 t0, COP_0_STATUS_REG + mtc0 t0, MIPS_COP_0_STATUS PTR_ADDU a0, k1, U_PCB_REGS ITLBNOPFIX @@ -521,10 +521,10 @@ NNON_LEAF(MipsUserGenException, CALLFRAM * Some of interrupts could be enabled by ithread * scheduled by ast() */ - mfc0 a0, COP_0_STATUS_REG - and a0, a0, SR_INT_MASK + mfc0 a0, MIPS_COP_0_STATUS + and a0, a0, MIPS_SR_INT_MASK RESTORE_U_PCB_REG(a1, SR, k1) - and a1, a1, ~SR_INT_MASK + and a1, a1, ~MIPS_SR_INT_MASK or a1, a1, a0 SAVE_U_PCB_REG(a1, SR, k1) @@ -534,7 +534,7 @@ NNON_LEAF(MipsUserGenException, CALLFRAM mthi t1 RESTORE_U_PCB_REG(a0, PC, k1) RESTORE_U_PCB_REG(v0, V0, k1) - MTC0 a0, COP_0_EXC_PC # set return address + MTC0 a0, MIPS_COP_0_EXC_PC # set return address RESTORE_U_PCB_REG(v1, V1, k1) RESTORE_U_PCB_REG(a0, A0, k1) RESTORE_U_PCB_REG(a1, A1, k1) @@ -566,7 +566,7 @@ NNON_LEAF(MipsUserGenException, CALLFRAM .set noat RESTORE_U_PCB_REG(AT, AST, k1) - mtc0 k0, COP_0_STATUS_REG # still exception level + mtc0 k0, MIPS_COP_0_STATUS # still exception level ITLBNOPFIX sync eret @@ -612,10 +612,10 @@ NNON_LEAF(MipsKernIntr, KERN_EXC_FRAME_S * intr filters if interrupts are enabled later * in trap handler */ - mfc0 a0, COP_0_STATUS_REG - and a0, a0, SR_INT_MASK + mfc0 a0, MIPS_COP_0_STATUS + and a0, a0, MIPS_SR_INT_MASK RESTORE_REG(a1, SR, sp) - and a1, a1, ~SR_INT_MASK + and a1, a1, ~MIPS_SR_INT_MASK or a1, a1, a0 SAVE_REG(a1, SR, sp) REG_L v0, CALLFRAME_RA + KERN_REG_SIZE(sp) @@ -689,9 +689,9 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, r mflo v0 # get lo/hi late to avoid stall mfhi v1 - mfc0 a0, COP_0_STATUS_REG - mfc0 a1, COP_0_CAUSE_REG - MFC0 a3, COP_0_EXC_PC + mfc0 a0, MIPS_COP_0_STATUS + mfc0 a1, MIPS_COP_0_CAUSE + MFC0 a3, MIPS_COP_0_EXC_PC SAVE_U_PCB_REG(v0, MULLO, k1) SAVE_U_PCB_REG(v1, MULHI, k1) SAVE_U_PCB_REG(a0, SR, k1) @@ -701,13 +701,13 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, r PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP # Turn off fpu, disable interrupts, set kernel mode kernel mode, clear exception level. - and t0, a0, ~(SR_COP_1_BIT | SR_EXL | SR_INT_ENAB | SR_KSU_MASK) + and t0, a0, ~(MIPS_SR_COP_1_BIT | MIPS_SR_EXL | MIPS_SR_INT_IE | MIPS3_SR_KSU_MASK) #ifdef TARGET_OCTEON - or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS32_SR_PX) + or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS_SR_PX) #elif defined(TARGET_XLR_XLS) or t0, t0, (MIPS_SR_KX | MIPS_SR_COP_2_BIT) #endif - mtc0 t0, COP_0_STATUS_REG + mtc0 t0, MIPS_COP_0_STATUS ITLBNOPFIX PTR_ADDU a0, k1, U_PCB_REGS /* @@ -724,9 +724,9 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, r * If that processor is also doing AST processing with interrupts disabled * then we may deadlock. */ - mfc0 a0, COP_0_STATUS_REG - or a0, a0, SR_INT_ENAB - mtc0 a0, COP_0_STATUS_REG + mfc0 a0, MIPS_COP_0_STATUS + or a0, a0, MIPS_SR_INT_IE + mtc0 a0, MIPS_COP_0_STATUS ITLBNOPFIX /* @@ -747,10 +747,10 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, r * Some of interrupts could be disabled by * intr filters */ - mfc0 a0, COP_0_STATUS_REG - and a0, a0, SR_INT_MASK + mfc0 a0, MIPS_COP_0_STATUS + and a0, a0, MIPS_SR_INT_MASK RESTORE_U_PCB_REG(a1, SR, k1) - and a1, a1, ~SR_INT_MASK + and a1, a1, ~MIPS_SR_INT_MASK or a1, a1, a0 SAVE_U_PCB_REG(a1, SR, k1) @@ -768,7 +768,7 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, r RESTORE_U_PCB_REG(t2, PC, k1) mtlo t0 mthi t1 - MTC0 t2, COP_0_EXC_PC # set return address + MTC0 t2, MIPS_COP_0_EXC_PC # set return address RESTORE_U_PCB_REG(v0, V0, k1) RESTORE_U_PCB_REG(v1, V1, k1) RESTORE_U_PCB_REG(a0, A0, k1) @@ -792,7 +792,7 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, r .set noat RESTORE_U_PCB_REG(AT, AST, k1) - mtc0 k0, COP_0_STATUS_REG # SR with EXL set. + mtc0 k0, MIPS_COP_0_STATUS # SR with EXL set. ITLBNOPFIX sync eret @@ -804,7 +804,7 @@ NLEAF(MipsTLBInvalidException) .set noat .set noreorder - MFC0 k0, COP_0_BAD_VADDR + MFC0 k0, MIPS_COP_0_BAD_VADDR PTR_LI k1, VM_MAXUSER_ADDRESS sltu k1, k0, k1 bnez k1, 1f @@ -833,7 +833,7 @@ NLEAF(MipsTLBInvalidException) beqz k1, 3f nop - MFC0 k0, COP_0_BAD_VADDR # k0=bad address (again) + MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address (again) PTR_SRL k0, PAGE_SHIFT - 2 # k0=VPN andi k0, k0, 0xffc # k0=page tab offset PTR_ADDU k1, k1, k0 # k1=pte address @@ -852,10 +852,10 @@ NLEAF(MipsTLBInvalidException) lw k0, 0(k1) lw k1, 4(k1) CLEAR_PTE_SWBITS(k0) - MTC0 k0, COP_0_TLB_LO0 + MTC0 k0, MIPS_COP_0_TLB_LO0 COP0_SYNC CLEAR_PTE_SWBITS(k1) - MTC0 k1, COP_0_TLB_LO1 + MTC0 k1, MIPS_COP_0_TLB_LO1 COP0_SYNC b tlb_insert_entry @@ -865,16 +865,16 @@ odd_page: lw k0, -4(k1) lw k1, 0(k1) CLEAR_PTE_SWBITS(k0) - MTC0 k0, COP_0_TLB_LO0 + MTC0 k0, MIPS_COP_0_TLB_LO0 COP0_SYNC CLEAR_PTE_SWBITS(k1) - MTC0 k1, COP_0_TLB_LO1 + MTC0 k1, MIPS_COP_0_TLB_LO1 COP0_SYNC tlb_insert_entry: tlbp HAZARD_DELAY - mfc0 k0, COP_0_TLB_INDEX + mfc0 k0, MIPS_COP_0_TLB_INDEX bltz k0, tlb_insert_random nop tlbwi @@ -890,7 +890,7 @@ tlb_insert_random: /* * Branch to the comprehensive exception processing. */ - mfc0 k1, COP_0_STATUS_REG + mfc0 k1, MIPS_COP_0_STATUS andi k1, k1, SR_KSU_USER bnez k1, _C_LABEL(MipsUserGenException) nop @@ -980,7 +980,7 @@ END(MipsTLBInvalidException) */ NLEAF(MipsTLBMissException) .set noat - MFC0 k0, COP_0_BAD_VADDR # k0=bad address + MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address PTR_LI k1, VM_MAX_KERNEL_ADDRESS # check fault address against sltu k1, k1, k0 # upper bound of kernel_segmap bnez k1, MipsKernGenException # out of bound @@ -991,7 +991,7 @@ NLEAF(MipsTLBMissException) andi k0, k0, PTRMASK # k0=seg offset PTR_ADDU k1, k0, k1 # k1=seg entry address PTR_L k1, 0(k1) # k1=seg entry - MFC0 k0, COP_0_BAD_VADDR # k0=bad address (again) + MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address (again) beq k1, zero, MipsKernGenException # ==0 -- no page table PTR_SRL k0, PAGE_SHIFT - 2 # k0=VPN andi k0, k0, 0xff8 # k0=page tab offset @@ -999,10 +999,10 @@ NLEAF(MipsTLBMissException) lw k0, 0(k1) # k0=lo0 pte lw k1, 4(k1) # k1=lo1 pte CLEAR_PTE_SWBITS(k0) - MTC0 k0, COP_0_TLB_LO0 # lo0 is loaded + MTC0 k0, MIPS_COP_0_TLB_LO0 # lo0 is loaded COP0_SYNC CLEAR_PTE_SWBITS(k1) - MTC0 k1, COP_0_TLB_LO1 # lo1 is loaded + MTC0 k1, MIPS_COP_0_TLB_LO1 # lo1 is loaded COP0_SYNC tlbwr # write to tlb HAZARD_DELAY @@ -1031,15 +1031,15 @@ END(MipsTLBMissException) */ NON_LEAF(MipsFPTrap, CALLFRAME_SIZ, ra) PTR_SUBU sp, sp, CALLFRAME_SIZ - mfc0 t0, COP_0_STATUS_REG + mfc0 t0, MIPS_COP_0_STATUS REG_S ra, CALLFRAME_RA(sp) .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ) - or t1, t0, SR_COP_1_BIT - mtc0 t1, COP_0_STATUS_REG + or t1, t0, MIPS_SR_COP_1_BIT + mtc0 t1, MIPS_COP_0_STATUS ITLBNOPFIX - cfc1 t1, FPC_CSR # stall til FP done - cfc1 t1, FPC_CSR # now get status + cfc1 t1, MIPS_FPU_CSR # stall til FP done + cfc1 t1, MIPS_FPU_CSR # now get status nop sll t2, t1, (31 - 17) # unimplemented operation? bgez t2, 3f # no, normal trap @@ -1087,8 +1087,8 @@ NON_LEAF(MipsFPTrap, CALLFRAME_SIZ, ra) * Check to see if the instruction to be emulated is a floating-point * instruction. */ - srl a3, a0, OPCODE_SHIFT - beq a3, OPCODE_C1, 4f # this should never fail + srl a3, a0, MIPS_OPCODE_SHIFT + beq a3, MIPS_OPCODE_C1, 4f # this should never fail nop /* * Send a floating point exception signal to the current process. @@ -1096,8 +1096,8 @@ NON_LEAF(MipsFPTrap, CALLFRAME_SIZ, ra) 3: GET_CPU_PCPU(a0) PTR_L a0, PC_CURTHREAD(a0) # get current thread - cfc1 a2, FPC_CSR # code = FP execptions - ctc1 zero, FPC_CSR # Clear exceptions + cfc1 a2, MIPS_FPU_CSR # code = FP execptions + ctc1 zero, MIPS_FPU_CSR # Clear exceptions PTR_LA t3, _C_LABEL(trapsignal) jalr t3 li a1, SIGFPE @@ -1116,10 +1116,10 @@ NON_LEAF(MipsFPTrap, CALLFRAME_SIZ, ra) * Turn off the floating point coprocessor and return. */ FPReturn: - mfc0 t0, COP_0_STATUS_REG + mfc0 t0, MIPS_COP_0_STATUS PTR_L ra, CALLFRAME_RA(sp) - and t0, t0, ~SR_COP_1_BIT - mtc0 t0, COP_0_STATUS_REG + and t0, t0, ~MIPS_SR_COP_1_BIT + mtc0 t0, MIPS_COP_0_STATUS ITLBNOPFIX j ra PTR_ADDU sp, sp, CALLFRAME_SIZ @@ -1168,15 +1168,15 @@ NESTED_NOPROFILE(MipsCacheException, KER .mask 0x80000000, -4 PTR_LA k0, _C_LABEL(panic) # return to panic PTR_LA a0, 9f # panicstr - MFC0 a1, COP_0_ERROR_PC - mfc0 a2, COP_0_CACHE_ERR # 3rd arg cache error + MFC0 a1, MIPS_COP_0_ERROR_PC + mfc0 a2, MIPS_COP_0_CACHE_ERR # 3rd arg cache error - MTC0 k0, COP_0_ERROR_PC # set return address + MTC0 k0, MIPS_COP_0_ERROR_PC # set return address - mfc0 k0, COP_0_STATUS_REG # restore status - li k1, SR_DIAG_DE # ignore further errors + mfc0 k0, MIPS_COP_0_STATUS # restore status + li k1, MIPS_SR_DIAG_PE # ignore further errors or k0, k1 - mtc0 k0, COP_0_STATUS_REG # restore status + mtc0 k0, MIPS_COP_0_STATUS # restore status COP0_SYNC eret Modified: head/sys/mips/mips/fp.S ============================================================================== --- head/sys/mips/mips/fp.S Tue Jul 13 23:58:10 2010 (r210037) +++ head/sys/mips/mips/fp.S Wed Jul 14 00:41:22 2010 (r210038) @@ -41,7 +41,7 @@ #include <machine/asm.h> #include <machine/regnum.h> -#include <machine/cpu.h> +#include <machine/cpuregs.h> #include "assym.s" @@ -107,10 +107,10 @@ NON_LEAF(MipsEmulateFP, CALLFRAME_SIZ, r bgt v0, 4 << 2, ill # illegal format or v1, v1, v0 - cfc1 a1, FPC_CSR # get exception register + cfc1 a1, MIPS_FPU_CSR # get exception register lw a3, func_fmt_tbl(v1) # switch on FUNC & FMT - and a1, a1, ~FPC_EXCEPTION_UNIMPL # clear exception - ctc1 a1, FPC_CSR + and a1, a1, ~MIPS_FPU_EXCEPTION_UNIMPL # clear exception + ctc1 a1, MIPS_FPU_CSR j a3 .rdata @@ -665,8 +665,8 @@ add_sub_s: 3: bne ta1, zero, result_ft_s # if FT != 0, result=FT bne ta2, zero, result_ft_s - and v0, a1, FPC_ROUNDING_BITS # get rounding mode - bne v0, FPC_ROUND_RM, 1f # round to -infinity? + and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode + bne v0, MIPS_FPU_ROUND_RM, 1f # round to -infinity? or t0, t0, ta0 # compute result sign b result_fs_s 1: @@ -724,8 +724,8 @@ add_sub_s: bne t2, ta2, 2f # if same, result=0 move t1, zero # result=0 move t2, zero - and v0, a1, FPC_ROUNDING_BITS # get rounding mode - bne v0, FPC_ROUND_RM, 1f # round to -infinity? + and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode + bne v0, MIPS_FPU_ROUND_RM, 1f # round to -infinity? or t0, t0, ta0 # compute result sign b result_fs_s 1: @@ -788,8 +788,8 @@ add_sub_d: bne ta1, zero, result_ft_d # if FT != 0, result=FT bne ta2, zero, result_ft_d bne ta3, zero, result_ft_d - and v0, a1, FPC_ROUNDING_BITS # get rounding mode - bne v0, FPC_ROUND_RM, 1f # round to -infinity? + and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode + bne v0, MIPS_FPU_ROUND_RM, 1f # round to -infinity? or t0, t0, ta0 # compute result sign b result_fs_d 1: @@ -882,8 +882,8 @@ add_sub_d: move t1, zero # result=0 move t2, zero move t3, zero - and v0, a1, FPC_ROUNDING_BITS # get rounding mode - bne v0, FPC_ROUND_RM, 1f # round to -infinity? + and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode + bne v0, MIPS_FPU_ROUND_RM, 1f # round to -infinity? or t0, t0, ta0 # compute result sign b result_fs_d 1: @@ -1078,10 +1078,10 @@ div_s: 3: bne ta1, zero, 2f # is FT zero? bne ta2, zero, 1f - or a1, a1, FPC_EXCEPTION_DIV0 | FPC_STICKY_DIV0 - and v0, a1, FPC_ENABLE_DIV0 # trap enabled? + or a1, a1, MIPS_FPU_EXCEPTION_DIV0 | MIPS_FPU_STICKY_DIV0 + and v0, a1, MIPS_FPU_ENABLE_DIV0 # trap enabled? bne v0, zero, fpe_trap - ctc1 a1, FPC_CSR # save exceptions + ctc1 a1, MIPS_FPU_CSR # save exceptions li t1, SEXP_INF # result is infinity move t2, zero b result_fs_s @@ -1152,10 +1152,10 @@ div_d: bne ta1, zero, 2f # is FT zero? bne ta2, zero, 1f bne ta3, zero, 1f - or a1, a1, FPC_EXCEPTION_DIV0 | FPC_STICKY_DIV0 - and v0, a1, FPC_ENABLE_DIV0 # trap enabled? + or a1, a1, MIPS_FPU_EXCEPTION_DIV0 | MIPS_FPU_STICKY_DIV0 + and v0, a1, MIPS_FPU_ENABLE_DIV0 # trap enabled? bne v0, zero, fpe_trap - ctc1 a1, FPC_CSR # Save exceptions + ctc1 a1, MIPS_FPU_CSR # Save exceptions li t1, DEXP_INF # result is infinity move t2, zero move t3, zero @@ -1504,10 +1504,10 @@ cvt_w: * round result (t0 is sign, t2 is integer part, t3 is fractional part). */ 2: - and v0, a1, FPC_ROUNDING_BITS # get rounding mode - beq v0, FPC_ROUND_RN, 3f # round to nearest - beq v0, FPC_ROUND_RZ, 5f # round to zero (truncate) - beq v0, FPC_ROUND_RP, 1f # round to +infinity + and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode + beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest + beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate) + beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity beq t0, zero, 5f # if sign is positive, truncate b 2f 1: @@ -1536,10 +1536,10 @@ cvt_w: * Handle inexact exception. */ inexact_w: - or a1, a1, FPC_EXCEPTION_INEXACT | FPC_STICKY_INEXACT - and v0, a1, FPC_ENABLE_INEXACT + or a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT + and v0, a1, MIPS_FPU_ENABLE_INEXACT bne v0, zero, fpe_trap - ctc1 a1, FPC_CSR # save exceptions + ctc1 a1, MIPS_FPU_CSR # save exceptions b result_fs_w /* @@ -1548,10 +1548,10 @@ inexact_w: * or generate an invalid exception. */ overflow_w: - or a1, a1, FPC_EXCEPTION_OVERFLOW | FPC_STICKY_OVERFLOW - and v0, a1, FPC_ENABLE_OVERFLOW + or a1, a1, MIPS_FPU_EXCEPTION_OVERFLOW | MIPS_FPU_STICKY_OVERFLOW + and v0, a1, MIPS_FPU_ENABLE_OVERFLOW bne v0, zero, fpe_trap - and v0, a1, FPC_ENABLE_INEXACT + and v0, a1, MIPS_FPU_ENABLE_INEXACT bne v0, zero, inexact_w # inexact traps enabled? b invalid_w @@ -1561,10 +1561,10 @@ overflow_w: * or generate an invalid exception. */ underflow_w: - or a1, a1, FPC_EXCEPTION_UNDERFLOW | FPC_STICKY_UNDERFLOW - and v0, a1, FPC_ENABLE_UNDERFLOW + or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW + and v0, a1, MIPS_FPU_ENABLE_UNDERFLOW bne v0, zero, fpe_trap - and v0, a1, FPC_ENABLE_INEXACT + and v0, a1, MIPS_FPU_ENABLE_INEXACT bne v0, zero, inexact_w # inexact traps enabled? b invalid_w @@ -1640,29 +1640,29 @@ test_cond: and v0, v0, a0 # condition match instruction? set_cond: bne v0, zero, 1f - and a1, a1, ~FPC_COND_BIT # clear condition bit + and a1, a1, ~MIPS_FPU_COND_BIT # clear condition bit b 2f 1: - or a1, a1, FPC_COND_BIT # set condition bit + or a1, a1, MIPS_FPU_COND_BIT # set condition bit 2: - ctc1 a1, FPC_CSR # save condition bit + ctc1 a1, MIPS_FPU_CSR # save condition bit b done unordered: and v0, a0, COND_UNORDERED # this cmp match unordered? bne v0, zero, 1f - and a1, a1, ~FPC_COND_BIT # clear condition bit + and a1, a1, ~MIPS_FPU_COND_BIT # clear condition bit b 2f 1: - or a1, a1, FPC_COND_BIT # set condition bit + or a1, a1, MIPS_FPU_COND_BIT # set condition bit 2: and v0, a0, COND_SIGNAL beq v0, zero, 1f # is this a signaling cmp? - or a1, a1, FPC_EXCEPTION_INVALID | FPC_STICKY_INVALID - and v0, a1, FPC_ENABLE_INVALID + or a1, a1, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID + and v0, a1, MIPS_FPU_ENABLE_INVALID bne v0, zero, fpe_trap 1: - ctc1 a1, FPC_CSR # save condition bit + ctc1 a1, MIPS_FPU_CSR # save condition bit b done /* @@ -1727,10 +1727,10 @@ norm_s: norm_noshift_s: move ta1, t1 # save unrounded exponent move ta2, t2 # save unrounded fraction - and v0, a1, FPC_ROUNDING_BITS # get rounding mode - beq v0, FPC_ROUND_RN, 3f # round to nearest - beq v0, FPC_ROUND_RZ, 5f # round to zero (truncate) - beq v0, FPC_ROUND_RP, 1f # round to +infinity + and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode + beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest + beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate) + beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity beq t0, zero, 5f # if sign is positive, truncate b 2f 1: @@ -1770,10 +1770,10 @@ inexact_s: and t2, t2, ~SIMPL_ONE # clear implied one bit inexact_nobias_s: jal set_fd_s # save result - or a1, a1, FPC_EXCEPTION_INEXACT | FPC_STICKY_INEXACT - and v0, a1, FPC_ENABLE_INEXACT + or a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT + and v0, a1, MIPS_FPU_ENABLE_INEXACT bne v0, zero, fpe_trap - ctc1 a1, FPC_CSR # save exceptions + ctc1 a1, MIPS_FPU_CSR # save exceptions b done /* @@ -1782,18 +1782,18 @@ inexact_nobias_s: * or generate an infinity. */ overflow_s: - or a1, a1, FPC_EXCEPTION_OVERFLOW | FPC_STICKY_OVERFLOW - and v0, a1, FPC_ENABLE_OVERFLOW + or a1, a1, MIPS_FPU_EXCEPTION_OVERFLOW | MIPS_FPU_STICKY_OVERFLOW + and v0, a1, MIPS_FPU_ENABLE_OVERFLOW beq v0, zero, 1f subu t1, t1, 192 # bias exponent and t2, t2, ~SIMPL_ONE # clear implied one bit jal set_fd_s # save result b fpe_trap 1: - and v0, a1, FPC_ROUNDING_BITS # get rounding mode - beq v0, FPC_ROUND_RN, 3f # round to nearest - beq v0, FPC_ROUND_RZ, 1f # round to zero (truncate) - beq v0, FPC_ROUND_RP, 2f # round to +infinity + and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode + beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest + beq v0, MIPS_FPU_ROUND_RZ, 1f # round to zero (truncate) + beq v0, MIPS_FPU_ROUND_RP, 2f # round to +infinity bne t0, zero, 3f 1: li t1, SEXP_MAX # result is max finite @@ -1811,7 +1811,7 @@ overflow_s: * "loss of accuracy" is detected as "an inexact result". */ underflow_s: - and v0, a1, FPC_ENABLE_UNDERFLOW + and v0, a1, MIPS_FPU_ENABLE_UNDERFLOW beq v0, zero, 1f /* * Underflow is enabled so compute the result and trap. @@ -1819,7 +1819,7 @@ underflow_s: addu t1, t1, 192 # bias exponent and t2, t2, ~SIMPL_ONE # clear implied one bit jal set_fd_s # save result - or a1, a1, FPC_EXCEPTION_UNDERFLOW | FPC_STICKY_UNDERFLOW + or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW b fpe_trap /* * Underflow is not enabled so compute the result, @@ -1833,15 +1833,15 @@ underflow_s: blt t9, SFRAC_BITS+2, 3f # shift all the bits out? move t1, zero # result is inexact zero move t2, zero - or a1, a1, FPC_EXCEPTION_UNDERFLOW | FPC_STICKY_UNDERFLOW + or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW /* * Now round the zero result. * Only need to worry about rounding to +- infinity when the sign matches. */ - and v0, a1, FPC_ROUNDING_BITS # get rounding mode - beq v0, FPC_ROUND_RN, inexact_nobias_s # round to nearest - beq v0, FPC_ROUND_RZ, inexact_nobias_s # round to zero - beq v0, FPC_ROUND_RP, 1f # round to +infinity + and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode + beq v0, MIPS_FPU_ROUND_RN, inexact_nobias_s # round to nearest + beq v0, MIPS_FPU_ROUND_RZ, inexact_nobias_s # round to zero + beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity beq t0, zero, inexact_nobias_s # if sign is positive, truncate b 2f 1: @@ -1859,10 +1859,10 @@ underflow_s: /* * Now round the denormalized result. */ - and v0, a1, FPC_ROUNDING_BITS # get rounding mode - beq v0, FPC_ROUND_RN, 3f # round to nearest - beq v0, FPC_ROUND_RZ, 5f # round to zero (truncate) - beq v0, FPC_ROUND_RP, 1f # round to +infinity + and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode + beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest + beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate) + beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity beq t0, zero, 5f # if sign is positive, truncate b 2f 1: @@ -1884,11 +1884,11 @@ underflow_s: move t1, zero # denorm or zero exponent jal set_fd_s # save result beq t8, zero, done # check for exact result - or a1, a1, FPC_EXCEPTION_UNDERFLOW | FPC_STICKY_UNDERFLOW - or a1, a1, FPC_EXCEPTION_INEXACT | FPC_STICKY_INEXACT - and v0, a1, FPC_ENABLE_INEXACT + or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW + or a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT + and v0, a1, MIPS_FPU_ENABLE_INEXACT bne v0, zero, fpe_trap - ctc1 a1, FPC_CSR # save exceptions + ctc1 a1, MIPS_FPU_CSR # save exceptions b done /* @@ -1973,10 +1973,10 @@ norm_noshift_d: move ta1, t1 # save unrounded exponent move ta2, t2 # save unrounded fraction (MS) move ta3, t3 # save unrounded fraction (LS) - and v0, a1, FPC_ROUNDING_BITS # get rounding mode - beq v0, FPC_ROUND_RN, 3f # round to nearest - beq v0, FPC_ROUND_RZ, 5f # round to zero (truncate) - beq v0, FPC_ROUND_RP, 1f # round to +infinity + and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode + beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest + beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate) + beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity beq t0, zero, 5f # if sign is positive, truncate b 2f 1: @@ -2020,10 +2020,10 @@ inexact_d: and t2, t2, ~DIMPL_ONE # clear implied one bit inexact_nobias_d: jal set_fd_d # save result - or a1, a1, FPC_EXCEPTION_INEXACT | FPC_STICKY_INEXACT - and v0, a1, FPC_ENABLE_INEXACT + or a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT + and v0, a1, MIPS_FPU_ENABLE_INEXACT bne v0, zero, fpe_trap - ctc1 a1, FPC_CSR # save exceptions + ctc1 a1, MIPS_FPU_CSR # save exceptions b done /* @@ -2032,18 +2032,18 @@ inexact_nobias_d: * or generate an infinity. */ overflow_d: - or a1, a1, FPC_EXCEPTION_OVERFLOW | FPC_STICKY_OVERFLOW - and v0, a1, FPC_ENABLE_OVERFLOW + or a1, a1, MIPS_FPU_EXCEPTION_OVERFLOW | MIPS_FPU_STICKY_OVERFLOW + and v0, a1, MIPS_FPU_ENABLE_OVERFLOW beq v0, zero, 1f subu t1, t1, 1536 # bias exponent and t2, t2, ~DIMPL_ONE # clear implied one bit jal set_fd_d # save result b fpe_trap 1: - and v0, a1, FPC_ROUNDING_BITS # get rounding mode - beq v0, FPC_ROUND_RN, 3f # round to nearest - beq v0, FPC_ROUND_RZ, 1f # round to zero (truncate) - beq v0, FPC_ROUND_RP, 2f # round to +infinity + and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode + beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest + beq v0, MIPS_FPU_ROUND_RZ, 1f # round to zero (truncate) + beq v0, MIPS_FPU_ROUND_RP, 2f # round to +infinity bne t0, zero, 3f 1: li t1, DEXP_MAX # result is max finite @@ -2063,7 +2063,7 @@ overflow_d: * "loss of accuracy" is detected as "an inexact result". */ underflow_d: - and v0, a1, FPC_ENABLE_UNDERFLOW + and v0, a1, MIPS_FPU_ENABLE_UNDERFLOW beq v0, zero, 1f /* * Underflow is enabled so compute the result and trap. @@ -2071,7 +2071,7 @@ underflow_d: addu t1, t1, 1536 # bias exponent and t2, t2, ~DIMPL_ONE # clear implied one bit jal set_fd_d # save result - or a1, a1, FPC_EXCEPTION_UNDERFLOW | FPC_STICKY_UNDERFLOW + or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW b fpe_trap /* * Underflow is not enabled so compute the result, @@ -2087,15 +2087,15 @@ underflow_d: move t1, zero # result is inexact zero move t2, zero move t3, zero - or a1, a1, FPC_EXCEPTION_UNDERFLOW | FPC_STICKY_UNDERFLOW + or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW /* * Now round the zero result. * Only need to worry about rounding to +- infinity when the sign matches. */ - and v0, a1, FPC_ROUNDING_BITS # get rounding mode - beq v0, FPC_ROUND_RN, inexact_nobias_d # round to nearest - beq v0, FPC_ROUND_RZ, inexact_nobias_d # round to zero - beq v0, FPC_ROUND_RP, 1f # round to +infinity + and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode + beq v0, MIPS_FPU_ROUND_RN, inexact_nobias_d # round to nearest + beq v0, MIPS_FPU_ROUND_RZ, inexact_nobias_d # round to zero + beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity beq t0, zero, inexact_nobias_d # if sign is positive, truncate b 2f 1: @@ -2127,10 +2127,10 @@ underflow_d: * Now round the denormalized result. */ 2: - and v0, a1, FPC_ROUNDING_BITS # get rounding mode - beq v0, FPC_ROUND_RN, 3f # round to nearest - beq v0, FPC_ROUND_RZ, 5f # round to zero (truncate) - beq v0, FPC_ROUND_RP, 1f # round to +infinity + and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode + beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest + beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate) + beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity beq t0, zero, 5f # if sign is positive, truncate b 2f 1: @@ -2156,11 +2156,11 @@ underflow_d: move t1, zero # denorm or zero exponent jal set_fd_d # save result beq t8, zero, done # check for exact result - or a1, a1, FPC_EXCEPTION_UNDERFLOW | FPC_STICKY_UNDERFLOW - or a1, a1, FPC_EXCEPTION_INEXACT | FPC_STICKY_INEXACT - and v0, a1, FPC_ENABLE_INEXACT + or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW + or a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT + and v0, a1, MIPS_FPU_ENABLE_INEXACT bne v0, zero, fpe_trap - ctc1 a1, FPC_CSR # save exceptions + ctc1 a1, MIPS_FPU_CSR # save exceptions b done /* @@ -2168,10 +2168,10 @@ underflow_d: * the result is a quiet NAN. */ invalid_s: # trap invalid operation - or a1, a1, FPC_EXCEPTION_INVALID | FPC_STICKY_INVALID - and v0, a1, FPC_ENABLE_INVALID + or a1, a1, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID + and v0, a1, MIPS_FPU_ENABLE_INVALID bne v0, zero, fpe_trap - ctc1 a1, FPC_CSR # save exceptions + ctc1 a1, MIPS_FPU_CSR # save exceptions move t0, zero # result is a quiet NAN li t1, SEXP_INF li t2, SQUIET_NAN @@ -2183,10 +2183,10 @@ invalid_s: # trap invalid operation * the result is a quiet NAN. */ invalid_d: # trap invalid operation - or a1, a1, FPC_EXCEPTION_INVALID | FPC_STICKY_INVALID - and v0, a1, FPC_ENABLE_INVALID + or a1, a1, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID + and v0, a1, MIPS_FPU_ENABLE_INVALID bne v0, zero, fpe_trap - ctc1 a1, FPC_CSR # save exceptions + ctc1 a1, MIPS_FPU_CSR # save exceptions move t0, zero # result is a quiet NAN li t1, DEXP_INF li t2, DQUIET_NAN0 @@ -2199,10 +2199,10 @@ invalid_d: # trap invalid operation * the result is INT_MAX or INT_MIN. */ invalid_w: # trap invalid operation - or a1, a1, FPC_EXCEPTION_INVALID | FPC_STICKY_INVALID - and v0, a1, FPC_ENABLE_INVALID + or a1, a1, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID + and v0, a1, MIPS_FPU_ENABLE_INVALID bne v0, zero, fpe_trap - ctc1 a1, FPC_CSR # save exceptions + ctc1 a1, MIPS_FPU_CSR # save exceptions bne t0, zero, 1f li t2, INT_MAX # result is INT_MAX b result_fs_w @@ -2215,14 +2215,14 @@ invalid_w: # trap invalid operation */ fpe_trap: move a2, a1 # code = FP CSR - ctc1 a1, FPC_CSR # save exceptions + ctc1 a1, MIPS_FPU_CSR # save exceptions break 0 /* * Send an illegal instruction signal to the current process. */ ill: - ctc1 a1, FPC_CSR # save exceptions + ctc1 a1, MIPS_FPU_CSR # save exceptions move a2, a0 # code = FP instruction break 0 Modified: head/sys/mips/mips/machdep.c ============================================================================== --- head/sys/mips/mips/machdep.c Tue Jul 13 23:58:10 2010 (r210037) +++ head/sys/mips/mips/machdep.c Wed Jul 14 00:41:22 2010 (r210038) @@ -344,19 +344,19 @@ mips_vector_init(void) if (MipsCacheEnd - MipsCache > 0x80) panic("startup: Cache error code too large"); - bcopy(MipsTLBMiss, (void *)TLB_MISS_EXC_VEC, + bcopy(MipsTLBMiss, (void *)MIPS_UTLB_MISS_EXC_VEC, MipsTLBMissEnd - MipsTLBMiss); #if defined(TARGET_OCTEON) || defined(TARGET_XLR_XLS) /* Fake, but sufficient, for the 32-bit with 64-bit hardware addresses */ - bcopy(MipsTLBMiss, (void *)XTLB_MISS_EXC_VEC, + bcopy(MipsTLBMiss, (void *)MIPS3_XTLB_MISS_EXC_VEC, MipsTLBMissEnd - MipsTLBMiss); #endif - bcopy(MipsException, (void *)GEN_EXC_VEC, + bcopy(MipsException, (void *)MIPS3_GEN_EXC_VEC, MipsExceptionEnd - MipsException); - bcopy(MipsCache, (void *)CACHE_ERR_EXC_VEC, + bcopy(MipsCache, (void *)MIPS3_CACHE_ERR_EXC_VEC, MipsCacheEnd - MipsCache); *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
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