Date: Sat, 19 Jun 1999 11:07:36 -0600 From: Warner Losh <imp@harmony.village.org> To: Marc Nicholas <marc@netstor.com> Cc: Pat Lynch <lynch@bsdunix.net>, hackers@FreeBSD.ORG Subject: Re: SMP and Celerons... Message-ID: <199906191707.LAA86070@harmony.village.org> In-Reply-To: Your message of "Sat, 19 Jun 1999 13:03:10 EDT." <Pine.BSF.4.05.9906191302400.16699-100000@medulla.hippocampus.net> References: <Pine.BSF.4.05.9906191302400.16699-100000@medulla.hippocampus.net>
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In message <Pine.BSF.4.05.9906191302400.16699-100000@medulla.hippocampus.net> Marc Nicholas writes: : Hmmm...I always thought there was something "broke" inside Celerons to : prevent SMP...maybe I'm wrong? Sure would be neat if you could run them : SMP... What is "broke" about the Celerons is their cache. Without a good cache sharing, you can't get good SMP performance. While you can run a SMP Celeron machine, it won't scale as well as the PII version of the chip. Warner To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-hackers" in the body of the message
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