Date: Thu, 28 Nov 2013 11:23:37 +0200 From: Konstantin Belousov <kostikbel@gmail.com> To: Don Lewis <truckman@FreeBSD.org> Cc: pho@FreeBSD.org, freebsd-current@FreeBSD.org Subject: Re: panic: double fault with 11.0-CURRENT r258504 Message-ID: <20131128092337.GL59496@kib.kiev.ua> In-Reply-To: <201311280856.rAS8ubLR044563@gw.catspoiler.org> References: <20131128075610.GJ59496@kib.kiev.ua> <201311280856.rAS8ubLR044563@gw.catspoiler.org>
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On Thu, Nov 28, 2013 at 12:56:37AM -0800, Don Lewis wrote:
> I haven't figured out how to find the currently installed BIOS version.
> The motherboard is Abit, which is no more, but I found an archive of all
> of their downloads. I'll also check into updates from the Linux world.
I reviewed the 0xF family revision guide, and stumbled upon errata 122,
"TLB Flush Filter May Cause Coherency Problem in Multicore Systems".
You could try the patch at the end of message.
> This machine gets updated every month or so and I've never had stability
> problems with it until just recently. It's definitely been using clang
> for quite a while without any problems other than the ports mess.
Is it possible to bisect ?
diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c
index 34a362d..87e3f69 100644
--- a/sys/amd64/amd64/initcpu.c
+++ b/sys/amd64/amd64/initcpu.c
@@ -88,6 +88,11 @@ static void
init_amd(void)
{
=20
+ if (CPUID_TO_FAMILY(cpu_id) =3D=3D 0x9) {
+ if ((cpu_feature2 & CPUID2_HV) =3D=3D 0)
+ wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) | (1 << 6));
+ }
+
/*
* Work around Erratum 721 for Family 10h and 12h processors.
* These processors may incorrectly update the stack pointer
diff --git a/sys/i386/i386/initcpu.c b/sys/i386/i386/initcpu.c
index 71c57b2..662ea8e 100644
--- a/sys/i386/i386/initcpu.c
+++ b/sys/i386/i386/initcpu.c
@@ -651,6 +651,32 @@ init_transmeta(void)
}
#endif
=20
+static void
+init_amd(void)
+{
+
+#ifdef CPU_ATHLON_SSE_HACK
+ /*
+ * Sometimes the BIOS doesn't enable SSE instructions.
+ * According to AMD document 20734, the mobile Duron, the
+ * (mobile) Athlon 4 and the Athlon MP support SSE. These
+ * correspond to cpu_id 0x66X or 0x67X.
+ */
+ if ((cpu_feature & CPUID_XMM) =3D=3D 0 && ((cpu_id & ~0xf) =3D=3D 0x660 ||
+ (cpu_id & ~0xf) =3D=3D 0x670 || (cpu_id & ~0xf) =3D=3D 0x680)) {
+ u_int regs[4];
+
+ wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000);
+ do_cpuid(1, regs);
+ cpu_feature =3D regs[3];
+ }
+#endif
+ if (CPUID_TO_FAMILY(cpu_id) =3D=3D 0x9) {
+ if ((cpu_feature2 & CPUID2_HV) =3D=3D 0)
+ wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) | (1 << 6));
+ }
+}
+
/*
* Initialize CR4 (Control register 4) to enable SSE instructions.
*/
@@ -725,26 +751,9 @@ initializecpu(void)
break;
}
break;
-#ifdef CPU_ATHLON_SSE_HACK
case CPU_VENDOR_AMD:
- /*
- * Sometimes the BIOS doesn't enable SSE instructions.
- * According to AMD document 20734, the mobile
- * Duron, the (mobile) Athlon 4 and the Athlon MP
- * support SSE. These correspond to cpu_id 0x66X
- * or 0x67X.
- */
- if ((cpu_feature & CPUID_XMM) =3D=3D 0 &&
- ((cpu_id & ~0xf) =3D=3D 0x660 ||
- (cpu_id & ~0xf) =3D=3D 0x670 ||
- (cpu_id & ~0xf) =3D=3D 0x680)) {
- u_int regs[4];
- wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000);
- do_cpuid(1, regs);
- cpu_feature =3D regs[3];
- }
+ init_amd();
break;
-#endif
case CPU_VENDOR_CENTAUR:
init_via();
break;
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