Date: Sun, 24 Apr 2005 21:54:15 +1000 From: Matthew Sullivan <matthew@uq.edu.au> To: Andre Guibert de Bruet <andy@siliconlandmark.com> Cc: current@freebsd.org Subject: Re: SMP on Compaq DL380 Message-ID: <426B88E7.2080606@uq.edu.au> In-Reply-To: <20050424073914.F68772@lexi.siliconlandmark.com> References: <4267A1CF.3080903@uq.edu.au> <20050422190208.M68772@lexi.siliconlandmark.com> <426A20E5.5020604@uq.edu.au> <426B06F5.3030506@uq.edu.au> <426B68B6.7000709@fer.hr> <426B7776.6060908@uq.edu.au> <20050424073914.F68772@lexi.siliconlandmark.com>
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Andre Guibert de Bruet wrote:
>
> On Sun, 24 Apr 2005, Matthew Sullivan wrote:
>
>> Ivan Voras wrote:
>>
>>> Matthew Sullivan wrote:
>>>
>>>>> they're not mismatched? The easy way of doing this if your BIOS
>>>>> doesn't post this information is using a Knoppix LiveCD and doing
>>>>> a cat /proc/cpuinfo.
>>>>
>>>>
>>>> Ok can't do the knoppix thing atm, however...
>>>
>>>
>>> Would ports/misc/cpuid help?
>>
>>
>> Probably not much help...
>
>
> The utility that I was looking for is sysutils/x86info. Does it detect
> everything correctly?
No...
x86info v1.12b. Dave Jones 2001-2003
Feedback to <davej@redhat.com>.
Found 1 CPU, but found 2 CPUs in MPTable.
MP Table:
# APIC ID Version State Family Model Step Flags
# 0 0x10 BSP, usable 6 2 1 0x0381
# 0 0x10 AP, usable 6 8 6 0x383fbff
--------------------------------------------------------------------------
eax in: 0x00000000, eax = 00000002 ebx = 756e6547 ecx = 6c65746e edx =
49656e69
eax in: 0x00000001, eax = 00000683 ebx = 00000002 ecx = 00000000 edx =
0383f9ff
eax in: 0x00000002, eax = 03020101 ebx = 00000000 ecx = 00000000 edx =
0c040882
Family: 6 Model: 8 Stepping: 3 Type: 0 Brand: 2
CPU Model: Pentium III-M (Coppermine) [cB0] Original OEM
Feature flags:
Onboard FPU
Virtual Mode Extensions
Debugging Extensions
Page Size Extensions
Time Stamp Counter
Model-Specific Registers
Physical Address Extensions
Machine Check Architecture
CMPXCHG8 instruction
SYSENTER/SYSEXIT
Memory Type Range Registers
Page Global Enable
Machine Check Architecture
CMOV instruction
Page Attribute Table
36-bit PSEs
MMX support
FXSAVE and FXRESTORE instructions
SSE support
Extended feature flags:
Instruction TLB: 4KB pages, 4-way associative, 32 entries
Instruction TLB: 4MB pages, fully associative, 2 entries
Data TLB: 4KB pages, 4-way associative, 64 entries
L2 unified cache:
Size: 256KB 8-way associative.
line size=32 bytes.
L1 Instruction cache:
Size: 16KB 4-way associative.
line size=32 bytes.
Data TLB: 4MB pages, 4-way associative, 8 entries
L1 Data cache:
Size: 16KB 4-way associative.
line size=32 bytes.
/dev/cpu/0/msr: No such file or directory
MTRR registers:
MTRRcap (0xfe): MTRRphysBase0 (0x200): MTRRphysMask0 (0x201):
MTRRphysBase1 (0x202): MTRRphysMask1 (0x203): MTRRphysBase2 (0x204):
MTRRphysMask2 (0x205): MTRRphysBase3 (0x206): MTRRphysMask3 (0x207):
MTRRphysBase4 (0x208): MTRRphysMask4 (0x209): MTRRphysBase5 (0x20a):
MTRRphysMask5 (0x20b): MTRRphysBase6 (0x20c): MTRRphysMask6 (0x20d):
MTRRphysBase7 (0x20e): MTRRphysMask7 (0x20f): MTRRfix64K_00000 (0x250):
MTRRfix16K_80000 (0x258): MTRRfix16K_A0000 (0x259): MTRRfix4K_C8000
(0x269): MTRRfix4K_D0000 0x26a: MTRRfix4K_D8000 0x26b: MTRRfix4K_E0000
0x26c: MTRRfix4K_E8000 0x26d: MTRRfix4K_F0000 0x26e: MTRRfix4K_F8000
0x26f: MTRRdefType (0x2ff):
850MHz processor (estimate).
Regards,
--
Matthew Sullivan
Specialist Systems Programmer
Information Technology Services
The University of Queensland
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