Date: Wed, 2 May 2007 13:28:55 -0400 From: Jung-uk Kim <jkim@FreeBSD.org> To: freebsd-net@FreeBSD.org Subject: [PATCH] DMA R/W control for bge(4) Message-ID: <200705021329.02520.jkim@FreeBSD.org>
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--Boundary-00=_epMOGzyckSwJO5Z Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline This is a patch to correct DMA rwad/write control register settings. Actually it is all started from kern/96806: http://www.freebsd.org/cgi/query-pr.cgi?pr=96806 BCM5714C works now but we have some remaining patch in the PR. Please test the patch and let me know if it breaks anything. Thanks, Jung-uk Kim --Boundary-00=_epMOGzyckSwJO5Z Content-Type: text/x-diff; charset="iso-8859-1"; name="bge_dmarwctl.diff" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="bge_dmarwctl.diff" Index: sys/dev/bge/if_bge.c =================================================================== RCS file: /home/ncvs/src/sys/dev/bge/if_bge.c,v retrieving revision 1.91.2.22 diff -u -r1.91.2.22 if_bge.c --- sys/dev/bge/if_bge.c 13 Apr 2007 18:25:03 -0000 1.91.2.22 +++ sys/dev/bge/if_bge.c 2 May 2007 16:42:00 -0000 @@ -1121,60 +1121,60 @@ i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) BGE_MEMWIN_WRITE(sc, i, 0); - /* Set up the PCI DMA control register. */ + /* + * Set up the PCI DMA control register. + */ + dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | + BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); if (sc->bge_flags & BGE_FLAG_PCIE) { - /* PCI Express bus */ - dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | - BGE_PCIDMARWCTL_RD_WAT_SHIFT(0xF) | - BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x2); + /* Read watermark not used, 128 bytes for write. */ + dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); } else if (sc->bge_flags & BGE_FLAG_PCIX) { - /* PCI-X bus */ if (BGE_IS_5714_FAMILY(sc)) { - dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; - dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */ - /* XXX magic values, Broadcom-supplied Linux driver */ - dma_rw_ctl |= (1 << 20) | (1 << 18); - if (sc->bge_asicrev == BGE_ASICREV_BCM5780) - dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; - else - dma_rw_ctl |= 1 << 15; - - } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) - /* - * The 5704 uses a different encoding of read/write - * watermarks. - */ - dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | - BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x7) | - BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x3); - else - dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | - BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x3) | - BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x3) | + /* 256 bytes for read and write. */ + dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | + BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); + dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? + BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : + BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; + } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { + /* 1536 bytes for read, 384 bytes for write. */ + dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | + BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); + } else { + /* 384 bytes for read and write. */ + dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | + BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 0x0F; - - /* - * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround - * for hardware bugs. - */ + } if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || sc->bge_asicrev == BGE_ASICREV_BCM5704) { uint32_t tmp; + /* Set ONE_DMA_AT_ONCE for hardware workaround. */ tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; - if (tmp == 0x6 || tmp == 0x7) - dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; - } - } else - /* Conventional PCI bus */ - dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | - BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x7) | - BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x7) | - 0x0F; + if (tmp == 6 || tmp == 7) + dma_rw_ctl |= + BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; + /* Set PCI-X DMA write workaround. */ + dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; + } + } else { + /* Conventional PCI bus: 256 bytes for read and write. */ + dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | + BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); + + if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && + sc->bge_asicrev != BGE_ASICREV_BCM5750) + dma_rw_ctl |= 0x0F; + } + if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || + sc->bge_asicrev == BGE_ASICREV_BCM5701) + dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | + BGE_PCIDMARWCTL_ASRT_ALL_BE; if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || - sc->bge_asicrev == BGE_ASICREV_BCM5704 || - sc->bge_asicrev == BGE_ASICREV_BCM5705) + sc->bge_asicrev == BGE_ASICREV_BCM5704) dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); Index: sys/dev/bge/if_bgereg.h =================================================================== RCS file: /home/ncvs/src/sys/dev/bge/if_bgereg.h,v retrieving revision 1.36.2.10 diff -u -r1.36.2.10 if_bgereg.h --- sys/dev/bge/if_bgereg.h 21 Mar 2007 22:53:22 -0000 1.36.2.10 +++ sys/dev/bge/if_bgereg.h 2 May 2007 16:42:01 -0000 @@ -316,7 +316,9 @@ #define BGE_PCIDMARWCTL_MINDMA 0x000000FF #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 -#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 +#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 +#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 +#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000 @@ -2101,9 +2103,6 @@ #define BGE_MEDIA_COPPER 0x00000010 #define BGE_MEDIA_FIBER 0x00000020 -#define BGE_PCI_READ_CMD 0x06000000 -#define BGE_PCI_WRITE_CMD 0x70000000 - #define BGE_TICKS_PER_SEC 1000000 /* --Boundary-00=_epMOGzyckSwJO5Z--
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