Date: Wed, 16 Nov 2011 17:11:13 +0000 (UTC) From: Philip Paeps <philip@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r227569 - in head: share/man/man4 sys/conf sys/dev/sfxge sys/dev/sfxge/common sys/modules sys/modules/sfxge Message-ID: <201111161711.pAGHBDkq058627@svn.freebsd.org>
next in thread | raw e-mail | index | archive | help
Author: philip Date: Wed Nov 16 17:11:13 2011 New Revision: 227569 URL: http://svn.freebsd.org/changeset/base/227569 Log: Add the sfxge(4) device driver, providing support for 10Gb Ethernet adapters based on Solarflare SFC9000 family controllers. The driver supports jumbo frames, transmit/receive checksum offload, TCP Segmentation Offload (TSO), Large Receive Offload (LRO), VLAN checksum offload, VLAN TSO, and Receive Side Scaling (RSS) using MSI-X interrupts. This work was sponsored by Solarflare Communications, Inc. My sincere thanks to Ben Hutchings for doing a lot of the hard work! Sponsored by: Solarflare Communications, Inc. MFC after: 3 weeks Added: head/share/man/man4/sfxge.4 (contents, props changed) head/sys/dev/sfxge/ head/sys/dev/sfxge/common/ head/sys/dev/sfxge/common/efsys.h (contents, props changed) head/sys/dev/sfxge/common/efx.h (contents, props changed) head/sys/dev/sfxge/common/efx_bootcfg.c (contents, props changed) head/sys/dev/sfxge/common/efx_ev.c (contents, props changed) head/sys/dev/sfxge/common/efx_filter.c (contents, props changed) head/sys/dev/sfxge/common/efx_impl.h (contents, props changed) head/sys/dev/sfxge/common/efx_intr.c (contents, props changed) head/sys/dev/sfxge/common/efx_mac.c (contents, props changed) head/sys/dev/sfxge/common/efx_mcdi.c (contents, props changed) head/sys/dev/sfxge/common/efx_mcdi.h (contents, props changed) head/sys/dev/sfxge/common/efx_mon.c (contents, props changed) head/sys/dev/sfxge/common/efx_nic.c (contents, props changed) head/sys/dev/sfxge/common/efx_nvram.c (contents, props changed) head/sys/dev/sfxge/common/efx_phy.c (contents, props changed) head/sys/dev/sfxge/common/efx_port.c (contents, props changed) head/sys/dev/sfxge/common/efx_regs.h (contents, props changed) head/sys/dev/sfxge/common/efx_regs_ef10.h (contents, props changed) head/sys/dev/sfxge/common/efx_regs_mcdi.h (contents, props changed) head/sys/dev/sfxge/common/efx_regs_pci.h (contents, props changed) head/sys/dev/sfxge/common/efx_rx.c (contents, props changed) head/sys/dev/sfxge/common/efx_sram.c (contents, props changed) head/sys/dev/sfxge/common/efx_tx.c (contents, props changed) head/sys/dev/sfxge/common/efx_types.h (contents, props changed) head/sys/dev/sfxge/common/efx_vpd.c (contents, props changed) head/sys/dev/sfxge/common/efx_wol.c (contents, props changed) head/sys/dev/sfxge/common/siena_flash.h (contents, props changed) head/sys/dev/sfxge/common/siena_impl.h (contents, props changed) head/sys/dev/sfxge/common/siena_mac.c (contents, props changed) head/sys/dev/sfxge/common/siena_mon.c (contents, props changed) head/sys/dev/sfxge/common/siena_nic.c (contents, props changed) head/sys/dev/sfxge/common/siena_nvram.c (contents, props changed) head/sys/dev/sfxge/common/siena_phy.c (contents, props changed) head/sys/dev/sfxge/common/siena_sram.c (contents, props changed) head/sys/dev/sfxge/common/siena_vpd.c (contents, props changed) head/sys/dev/sfxge/sfxge.c (contents, props changed) head/sys/dev/sfxge/sfxge.h (contents, props changed) head/sys/dev/sfxge/sfxge_dma.c (contents, props changed) head/sys/dev/sfxge/sfxge_ev.c (contents, props changed) head/sys/dev/sfxge/sfxge_intr.c (contents, props changed) head/sys/dev/sfxge/sfxge_mcdi.c (contents, props changed) head/sys/dev/sfxge/sfxge_port.c (contents, props changed) head/sys/dev/sfxge/sfxge_rx.c (contents, props changed) head/sys/dev/sfxge/sfxge_rx.h (contents, props changed) head/sys/dev/sfxge/sfxge_tx.c (contents, props changed) head/sys/dev/sfxge/sfxge_tx.h (contents, props changed) head/sys/modules/sfxge/ head/sys/modules/sfxge/Makefile (contents, props changed) Modified: head/share/man/man4/Makefile head/sys/conf/files head/sys/modules/Makefile Modified: head/share/man/man4/Makefile ============================================================================== --- head/share/man/man4/Makefile Wed Nov 16 16:46:09 2011 (r227568) +++ head/share/man/man4/Makefile Wed Nov 16 17:11:13 2011 (r227569) @@ -377,6 +377,7 @@ MAN= aac.4 \ send.4 \ ses.4 \ sf.4 \ + sfxge.4 \ sge.4 \ si.4 \ siba.4 \ Added: head/share/man/man4/sfxge.4 ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/share/man/man4/sfxge.4 Wed Nov 16 17:11:13 2011 (r227569) @@ -0,0 +1,92 @@ +.\" Copyright (c) 2011 Solarflare Communications, Inc. +.\" All rights reserved. +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +.\" SUCH DAMAGE. +.\" +.\" $FreeBSD$ +.\" +.Dd November 16, 2011 +.Dt SFXGE 4 +.Os +.Sh NAME +.Nm sfxge +.Nd "Solarflare 10Gb Ethernet adapter driver" +.Sh SYNOPSIS +To compile this driver into the kernel, +place the following lines in your +kernel configuration file: +.Bd -ragged -offset indent +.Cd "device sfxge" +.Ed +.Pp +To load the driver as a +module at boot time, place the following line in +.Xr loader.conf 5 : +.Bd -literal -offset indent +sfxge_load="YES" +.Ed +.Sh DESCRIPTION +The +.Nm +driver provides support for 10Gb Ethernet adapters based on +Solarflare SFC9000 family controllers. The driver supports jumbo +frames, transmit/receive checksum offload, TCP Segmentation Offload +(TSO), Large Receive Offload (LRO), VLAN checksum offload, VLAN TSO, +and Receive Side Scaling (RSS) using MSI-X interrupts. +.Pp +The driver allocates 1 receive queue, transmit queue, event queue and +IRQ per CPU up to a maximum of 64. IRQ affinities should be spread +out using +.Xr cpuset 8 . +Interrupt moderation may be controlled through the sysctl +dev.sfxge.\fIindex\fR.int_mod (units are microseconds). +.Pp +For more information on configuring this device, see +.Xr ifconfig 8 . +.Pp +A large number of MAC, PHY and data path statistics are available +under the sysctl dev.sfxge.\fIindex\fR.stats. The adapter's VPD +fields including its serial number are available under the sysctl +dev.sfxge.\fIindex\fR.vpd. +.Sh HARDWARE +The +.Nm +driver supports all 10Gb Ethernet adapters based on Solarflare SFC9000 +family controllers. +.Sh SUPPORT +For general information and support, +go to the Solarflare support website at: +.Pa https://support.solarflare.com . +.Sh SEE ALSO +.Xr arp 4 , +.Xr netintro 4 , +.Xr ng_ether 4 , +.Xr vlan 4 , +.Xr cpuset 8 , +.Xr ifconfig 8 +.Sh AUTHORS +The +.Nm +driver was written by +.An Philip Paeps +and +.An Solarflare Communications, Inc. Modified: head/sys/conf/files ============================================================================== --- head/sys/conf/files Wed Nov 16 16:46:09 2011 (r227568) +++ head/sys/conf/files Wed Nov 16 17:11:13 2011 (r227569) @@ -1671,6 +1671,37 @@ dev/scd/scd.c optional scd isa dev/scd/scd_isa.c optional scd isa dev/sdhci/sdhci.c optional sdhci pci dev/sf/if_sf.c optional sf pci +dev/sfxge/common/efx_bootcfg.c optional sfxge inet pci +dev/sfxge/common/efx_ev.c optional sfxge inet pci +dev/sfxge/common/efx_filter.c optional sfxge inet pci +dev/sfxge/common/efx_intr.c optional sfxge inet pci +dev/sfxge/common/efx_mac.c optional sfxge inet pci +dev/sfxge/common/efx_mcdi.c optional sfxge inet pci +dev/sfxge/common/efx_mon.c optional sfxge inet pci +dev/sfxge/common/efx_nic.c optional sfxge inet pci +dev/sfxge/common/efx_nvram.c optional sfxge inet pci +dev/sfxge/common/efx_phy.c optional sfxge inet pci +dev/sfxge/common/efx_port.c optional sfxge inet pci +dev/sfxge/common/efx_rx.c optional sfxge inet pci +dev/sfxge/common/efx_sram.c optional sfxge inet pci +dev/sfxge/common/efx_tx.c optional sfxge inet pci +dev/sfxge/common/efx_vpd.c optional sfxge inet pci +dev/sfxge/common/efx_wol.c optional sfxge inet pci +dev/sfxge/common/siena_mac.c optional sfxge inet pci +dev/sfxge/common/siena_mon.c optional sfxge inet pci +dev/sfxge/common/siena_nic.c optional sfxge inet pci +dev/sfxge/common/siena_nvram.c optional sfxge inet pci +dev/sfxge/common/siena_phy.c optional sfxge inet pci +dev/sfxge/common/siena_sram.c optional sfxge inet pci +dev/sfxge/common/siena_vpd.c optional sfxge inet pci +dev/sfxge/sfxge.c optional sfxge inet pci +dev/sfxge/sfxge_dma.c optional sfxge inet pci +dev/sfxge/sfxge_ev.c optional sfxge inet pci +dev/sfxge/sfxge_intr.c optional sfxge inet pci +dev/sfxge/sfxge_mcdi.c optional sfxge inet pci +dev/sfxge/sfxge_port.c optional sfxge inet pci +dev/sfxge/sfxge_rx.c optional sfxge inet pci +dev/sfxge/sfxge_tx.c optional sfxge inet pci dev/sge/if_sge.c optional sge pci dev/si/si.c optional si dev/si/si2_z280.c optional si Added: head/sys/dev/sfxge/common/efsys.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/dev/sfxge/common/efsys.h Wed Nov 16 17:11:13 2011 (r227569) @@ -0,0 +1,800 @@ +/*- + * Copyright (c) 2010-2011 Solarflare Communications, Inc. + * All rights reserved. + * + * This software was developed in part by Philip Paeps under contract for + * Solarflare Communications, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _SYS_EFSYS_H +#define _SYS_EFSYS_H + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#ifdef __cplusplus +extern "C" { +#endif + +#include <sys/param.h> +#include <sys/bus.h> +#include <sys/endian.h> +#include <sys/lock.h> +#include <sys/malloc.h> +#include <sys/mbuf.h> +#include <sys/mutex.h> +#include <sys/rwlock.h> +#include <sys/sdt.h> +#include <sys/systm.h> + +#include <machine/bus.h> +#include <machine/endian.h> + +#define EFSYS_HAS_UINT64 1 +#define EFSYS_USE_UINT64 0 +#if _BYTE_ORDER == _BIG_ENDIAN +#define EFSYS_IS_BIG_ENDIAN 1 +#define EFSYS_IS_LITTLE_ENDIAN 0 +#elif _BYTE_ORDER == _LITTLE_ENDIAN +#define EFSYS_IS_BIG_ENDIAN 0 +#define EFSYS_IS_LITTLE_ENDIAN 1 +#endif +#include "efx_types.h" + +/* Common code requires this */ +#if __FreeBSD_version < 800068 +#define memmove(d, s, l) bcopy(s, d, l) +#endif + +/* FreeBSD equivalents of Solaris things */ +#ifndef _NOTE +#define _NOTE(s) +#endif + +#ifndef B_FALSE +#define B_FALSE FALSE +#endif +#ifndef B_TRUE +#define B_TRUE TRUE +#endif + +#ifndef IS_P2ALIGNED +#define IS_P2ALIGNED(v, a) ((((uintptr_t)(v)) & ((uintptr_t)(a) - 1)) == 0) +#endif + +#ifndef P2ROUNDUP +#define P2ROUNDUP(x, align) (-(-(x) & -(align))) +#endif + +#ifndef IS2P +#define ISP2(x) (((x) & ((x) - 1)) == 0) +#endif + +#define ENOTACTIVE EINVAL + +/* Memory type to use on FreeBSD */ +MALLOC_DECLARE(M_SFXGE); + +/* Machine dependend prefetch wrappers */ +#if defined(__i386) || defined(__amd64) +static __inline void +prefetch_read_many(void *addr) +{ + __asm__( + "prefetcht0 (%0)" + : + : "r" (addr)); +} + +static __inline void +prefetch_read_once(void *addr) +{ + __asm__( + "prefetchnta (%0)" + : + : "r" (addr)); +} +#endif + +#if defined(__i386__) || defined(__amd64__) +#include <vm/vm.h> +#include <vm/pmap.h> +#endif +static __inline void +sfxge_map_mbuf_fast(bus_dma_tag_t tag, bus_dmamap_t map, + struct mbuf *m, bus_dma_segment_t *seg) +{ +#if defined(__i386__) || defined(__amd64__) + seg->ds_addr = pmap_kextract(mtod(m, vm_offset_t)); + seg->ds_len = m->m_len; +#else + int nsegstmp; + + bus_dmamap_load_mbuf_sg(tag, map, m, seg, &nsegstmp, 0); +#endif +} + +/* Modifiers used for DOS builds */ +#define __cs +#define __far + +/* Modifiers used for Windows builds */ +#define __in +#define __in_opt +#define __in_ecount(_n) +#define __in_ecount_opt(_n) +#define __in_bcount(_n) +#define __in_bcount_opt(_n) + +#define __out +#define __out_opt +#define __out_ecount(_n) +#define __out_ecount_opt(_n) +#define __out_bcount(_n) +#define __out_bcount_opt(_n) + +#define __deref_out + +#define __inout +#define __inout_opt +#define __inout_ecount(_n) +#define __inout_ecount_opt(_n) +#define __inout_bcount(_n) +#define __inout_bcount_opt(_n) +#define __inout_bcount_full_opt(_n) + +#define __deref_out_bcount_opt(n) + +#define __checkReturn + +#define __drv_when(_p, _c) + +/* Code inclusion options */ + + +#define EFSYS_OPT_NAMES 1 + +#define EFSYS_OPT_FALCON 0 +#define EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE 0 +#define EFSYS_OPT_SIENA 1 +#ifdef DEBUG +#define EFSYS_OPT_CHECK_REG 1 +#else +#define EFSYS_OPT_CHECK_REG 0 +#endif + +#define EFSYS_OPT_MCDI 1 + +#define EFSYS_OPT_MAC_FALCON_GMAC 0 +#define EFSYS_OPT_MAC_FALCON_XMAC 0 +#define EFSYS_OPT_MAC_STATS 1 + +#define EFSYS_OPT_LOOPBACK 0 + +#define EFSYS_OPT_MON_NULL 0 +#define EFSYS_OPT_MON_LM87 0 +#define EFSYS_OPT_MON_MAX6647 0 +#define EFSYS_OPT_MON_SIENA 0 +#define EFSYS_OPT_MON_STATS 0 + +#define EFSYS_OPT_PHY_NULL 0 +#define EFSYS_OPT_PHY_QT2022C2 0 +#define EFSYS_OPT_PHY_SFX7101 0 +#define EFSYS_OPT_PHY_TXC43128 0 +#define EFSYS_OPT_PHY_PM8358 0 +#define EFSYS_OPT_PHY_SFT9001 0 +#define EFSYS_OPT_PHY_QT2025C 0 +#define EFSYS_OPT_PHY_STATS 1 +#define EFSYS_OPT_PHY_PROPS 0 +#define EFSYS_OPT_PHY_BIST 1 +#define EFSYS_OPT_PHY_LED_CONTROL 1 +#define EFSYS_OPT_PHY_FLAGS 0 + +#define EFSYS_OPT_VPD 1 +#define EFSYS_OPT_NVRAM 1 +#define EFSYS_OPT_NVRAM_FALCON_BOOTROM 0 +#define EFSYS_OPT_NVRAM_SFT9001 0 +#define EFSYS_OPT_NVRAM_SFX7101 0 +#define EFSYS_OPT_BOOTCFG 0 + +#define EFSYS_OPT_PCIE_TUNE 0 +#define EFSYS_OPT_DIAG 0 +#define EFSYS_OPT_WOL 1 +#define EFSYS_OPT_RX_SCALE 1 +#define EFSYS_OPT_QSTATS 1 +#define EFSYS_OPT_FILTER 0 +#define EFSYS_OPT_RX_SCATTER 0 +#define EFSYS_OPT_RX_HDR_SPLIT 0 + +#define EFSYS_OPT_EV_PREFETCH 0 + +#define EFSYS_OPT_DECODE_INTR_FATAL 1 + +/* ID */ + +typedef struct __efsys_identifier_s efsys_identifier_t; + +/* PROBE */ + +#ifndef KDTRACE_HOOKS + +#define EFSYS_PROBE(_name) + +#define EFSYS_PROBE1(_name, _type1, _arg1) + +#define EFSYS_PROBE2(_name, _type1, _arg1, _type2, _arg2) + +#define EFSYS_PROBE3(_name, _type1, _arg1, _type2, _arg2, \ + _type3, _arg3) + +#define EFSYS_PROBE4(_name, _type1, _arg1, _type2, _arg2, \ + _type3, _arg3, _type4, _arg4) + +#define EFSYS_PROBE5(_name, _type1, _arg1, _type2, _arg2, \ + _type3, _arg3, _type4, _arg4, _type5, _arg5) + +#define EFSYS_PROBE6(_name, _type1, _arg1, _type2, _arg2, \ + _type3, _arg3, _type4, _arg4, _type5, _arg5, \ + _type6, _arg6) + +#define EFSYS_PROBE7(_name, _type1, _arg1, _type2, _arg2, \ + _type3, _arg3, _type4, _arg4, _type5, _arg5, \ + _type6, _arg6, _type7, _arg7) + +#else /* KDTRACE_HOOKS */ + +#define EFSYS_PROBE(_name) \ + DTRACE_PROBE(_name) + +#define EFSYS_PROBE1(_name, _type1, _arg1) \ + DTRACE_PROBE1(_name, _type1, _arg1) + +#define EFSYS_PROBE2(_name, _type1, _arg1, _type2, _arg2) \ + DTRACE_PROBE2(_name, _type1, _arg1, _type2, _arg2) + +#define EFSYS_PROBE3(_name, _type1, _arg1, _type2, _arg2, \ + _type3, _arg3) \ + DTRACE_PROBE3(_name, _type1, _arg1, _type2, _arg2, \ + _type3, _arg3) + +#define EFSYS_PROBE4(_name, _type1, _arg1, _type2, _arg2, \ + _type3, _arg3, _type4, _arg4) \ + DTRACE_PROBE4(_name, _type1, _arg1, _type2, _arg2, \ + _type3, _arg3, _type4, _arg4) + +#ifdef DTRACE_PROBE5 +#define EFSYS_PROBE5(_name, _type1, _arg1, _type2, _arg2, \ + _type3, _arg3, _type4, _arg4, _type5, _arg5) \ + DTRACE_PROBE5(_name, _type1, _arg1, _type2, _arg2, \ + _type3, _arg3, _type4, _arg4, _type5, _arg5) +#else +#define EFSYS_PROBE5(_name, _type1, _arg1, _type2, _arg2, \ + _type3, _arg3, _type4, _arg4, _type5, _arg5) \ + DTRACE_PROBE4(_name, _type1, _arg1, _type2, _arg2, \ + _type3, _arg3, _type4, _arg4) +#endif + +#ifdef DTRACE_PROBE6 +#define EFSYS_PROBE6(_name, _type1, _arg1, _type2, _arg2, \ + _type3, _arg3, _type4, _arg4, _type5, _arg5, \ + _type6, _arg6) \ + DTRACE_PROBE6(_name, _type1, _arg1, _type2, _arg2, \ + _type3, _arg3, _type4, _arg4, _type5, _arg5, \ + _type6, _arg6) +#else +#define EFSYS_PROBE6(_name, _type1, _arg1, _type2, _arg2, \ + _type3, _arg3, _type4, _arg4, _type5, _arg5, \ + _type6, _arg6) \ + EFSYS_PROBE5(_name, _type1, _arg1, _type2, _arg2, \ + _type3, _arg3, _type4, _arg4, _type5, _arg5) +#endif + +#ifdef DTRACE_PROBE7 +#define EFSYS_PROBE7(_name, _type1, _arg1, _type2, _arg2, \ + _type3, _arg3, _type4, _arg4, _type5, _arg5, \ + _type6, _arg6, _type7, _arg7) \ + DTRACE_PROBE7(_name, _type1, _arg1, _type2, _arg2, \ + _type3, _arg3, _type4, _arg4, _type5, _arg5, \ + _type6, _arg6, _type7, _arg7) +#else +#define EFSYS_PROBE7(_name, _type1, _arg1, _type2, _arg2, \ + _type3, _arg3, _type4, _arg4, _type5, _arg5, \ + _type6, _arg6, _type7, _arg7) \ + EFSYS_PROBE6(_name, _type1, _arg1, _type2, _arg2, \ + _type3, _arg3, _type4, _arg4, _type5, _arg5, \ + _type6, _arg6) +#endif + +#endif /* KDTRACE_HOOKS */ + +/* DMA */ + +typedef uint64_t efsys_dma_addr_t; + +typedef struct efsys_mem_s { + bus_dma_tag_t esm_tag; + bus_dmamap_t esm_map; + caddr_t esm_base; + efsys_dma_addr_t esm_addr; + size_t esm_size; +} efsys_mem_t; + + +#define EFSYS_MEM_ZERO(_esmp, _size) \ + do { \ + (void) memset((_esmp)->esm_base, 0, (_size)); \ + \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_MEM_READD(_esmp, _offset, _edp) \ + do { \ + uint32_t *addr; \ + \ + _NOTE(CONSTANTCONDITION) \ + KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_dword_t)), \ + ("not power of 2 aligned")); \ + \ + addr = (void *)((_esmp)->esm_base + (_offset)); \ + \ + (_edp)->ed_u32[0] = *addr; \ + \ + EFSYS_PROBE2(mem_readd, unsigned int, (_offset), \ + uint32_t, (_edp)->ed_u32[0]); \ + \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_MEM_READQ(_esmp, _offset, _eqp) \ + do { \ + uint32_t *addr; \ + \ + _NOTE(CONSTANTCONDITION) \ + KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_qword_t)), \ + ("not power of 2 aligned")); \ + \ + addr = (void *)((_esmp)->esm_base + (_offset)); \ + \ + (_eqp)->eq_u32[0] = *addr++; \ + (_eqp)->eq_u32[1] = *addr; \ + \ + EFSYS_PROBE3(mem_readq, unsigned int, (_offset), \ + uint32_t, (_eqp)->eq_u32[1], \ + uint32_t, (_eqp)->eq_u32[0]); \ + \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_MEM_READO(_esmp, _offset, _eop) \ + do { \ + uint32_t *addr; \ + \ + _NOTE(CONSTANTCONDITION) \ + KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_oword_t)), \ + ("not power of 2 aligned")); \ + \ + addr = (void *)((_esmp)->esm_base + (_offset)); \ + \ + (_eop)->eo_u32[0] = *addr++; \ + (_eop)->eo_u32[1] = *addr++; \ + (_eop)->eo_u32[2] = *addr++; \ + (_eop)->eo_u32[3] = *addr; \ + \ + EFSYS_PROBE5(mem_reado, unsigned int, (_offset), \ + uint32_t, (_eop)->eo_u32[3], \ + uint32_t, (_eop)->eo_u32[2], \ + uint32_t, (_eop)->eo_u32[1], \ + uint32_t, (_eop)->eo_u32[0]); \ + \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_MEM_WRITED(_esmp, _offset, _edp) \ + do { \ + uint32_t *addr; \ + \ + _NOTE(CONSTANTCONDITION) \ + KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_dword_t)), \ + ("not power of 2 aligned")); \ + \ + EFSYS_PROBE2(mem_writed, unsigned int, (_offset), \ + uint32_t, (_edp)->ed_u32[0]); \ + \ + addr = (void *)((_esmp)->esm_base + (_offset)); \ + \ + *addr = (_edp)->ed_u32[0]; \ + \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_MEM_WRITEQ(_esmp, _offset, _eqp) \ + do { \ + uint32_t *addr; \ + \ + _NOTE(CONSTANTCONDITION) \ + KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_qword_t)), \ + ("not power of 2 aligned")); \ + \ + EFSYS_PROBE3(mem_writeq, unsigned int, (_offset), \ + uint32_t, (_eqp)->eq_u32[1], \ + uint32_t, (_eqp)->eq_u32[0]); \ + \ + addr = (void *)((_esmp)->esm_base + (_offset)); \ + \ + *addr++ = (_eqp)->eq_u32[0]; \ + *addr = (_eqp)->eq_u32[1]; \ + \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_MEM_WRITEO(_esmp, _offset, _eop) \ + do { \ + uint32_t *addr; \ + \ + _NOTE(CONSTANTCONDITION) \ + KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_oword_t)), \ + ("not power of 2 aligned")); \ + \ + EFSYS_PROBE5(mem_writeo, unsigned int, (_offset), \ + uint32_t, (_eop)->eo_u32[3], \ + uint32_t, (_eop)->eo_u32[2], \ + uint32_t, (_eop)->eo_u32[1], \ + uint32_t, (_eop)->eo_u32[0]); \ + \ + addr = (void *)((_esmp)->esm_base + (_offset)); \ + \ + *addr++ = (_eop)->eo_u32[0]; \ + *addr++ = (_eop)->eo_u32[1]; \ + *addr++ = (_eop)->eo_u32[2]; \ + *addr = (_eop)->eo_u32[3]; \ + \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_MEM_ADDR(_esmp) \ + ((_esmp)->esm_addr) + +/* BAR */ + +typedef struct efsys_bar_s { + struct mtx esb_lock; + bus_space_tag_t esb_tag; + bus_space_handle_t esb_handle; + int esb_rid; + struct resource *esb_res; +} efsys_bar_t; + +#define EFSYS_BAR_READD(_esbp, _offset, _edp, _lock) \ + do { \ + _NOTE(CONSTANTCONDITION) \ + KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_dword_t)), \ + ("not power of 2 aligned")); \ + \ + _NOTE(CONSTANTCONDITION) \ + if (_lock) \ + mtx_lock(&((_esbp)->esb_lock)); \ + \ + (_edp)->ed_u32[0] = bus_space_read_4((_esbp)->esb_tag, \ + (_esbp)->esb_handle, (_offset)); \ + \ + EFSYS_PROBE2(bar_readd, unsigned int, (_offset), \ + uint32_t, (_edp)->ed_u32[0]); \ + \ + _NOTE(CONSTANTCONDITION) \ + if (_lock) \ + mtx_unlock(&((_esbp)->esb_lock)); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_BAR_READQ(_esbp, _offset, _eqp) \ + do { \ + _NOTE(CONSTANTCONDITION) \ + KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_qword_t)), \ + ("not power of 2 aligned")); \ + \ + mtx_lock(&((_esbp)->esb_lock)); \ + \ + (_eqp)->eq_u32[0] = bus_space_read_4((_esbp)->esb_tag, \ + (_esbp)->esb_handle, (_offset)); \ + (_eqp)->eq_u32[1] = bus_space_read_4((_esbp)->esb_tag, \ + (_esbp)->esb_handle, (_offset+4)); \ + \ + EFSYS_PROBE3(bar_readq, unsigned int, (_offset), \ + uint32_t, (_eqp)->eq_u32[1], \ + uint32_t, (_eqp)->eq_u32[0]); \ + \ + mtx_unlock(&((_esbp)->esb_lock)); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_BAR_READO(_esbp, _offset, _eop, _lock) \ + do { \ + _NOTE(CONSTANTCONDITION) \ + KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_oword_t)), \ + ("not power of 2 aligned")); \ + \ + _NOTE(CONSTANTCONDITION) \ + if (_lock) \ + mtx_lock(&((_esbp)->esb_lock)); \ + \ + (_eop)->eo_u32[0] = bus_space_read_4((_esbp)->esb_tag, \ + (_esbp)->esb_handle, (_offset)); \ + (_eop)->eo_u32[1] = bus_space_read_4((_esbp)->esb_tag, \ + (_esbp)->esb_handle, (_offset+4)); \ + (_eop)->eo_u32[2] = bus_space_read_4((_esbp)->esb_tag, \ + (_esbp)->esb_handle, (_offset+8)); \ + (_eop)->eo_u32[3] = bus_space_read_4((_esbp)->esb_tag, \ + (_esbp)->esb_handle, (_offset+12)); \ + \ + EFSYS_PROBE5(bar_reado, unsigned int, (_offset), \ + uint32_t, (_eop)->eo_u32[3], \ + uint32_t, (_eop)->eo_u32[2], \ + uint32_t, (_eop)->eo_u32[1], \ + uint32_t, (_eop)->eo_u32[0]); \ + \ + _NOTE(CONSTANTCONDITION) \ + if (_lock) \ + mtx_unlock(&((_esbp)->esb_lock)); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_BAR_WRITED(_esbp, _offset, _edp, _lock) \ + do { \ + _NOTE(CONSTANTCONDITION) \ + KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_dword_t)), \ + ("not power of 2 aligned")); \ + \ + _NOTE(CONSTANTCONDITION) \ + if (_lock) \ + mtx_lock(&((_esbp)->esb_lock)); \ + \ + EFSYS_PROBE2(bar_writed, unsigned int, (_offset), \ + uint32_t, (_edp)->ed_u32[0]); \ + \ + bus_space_write_4((_esbp)->esb_tag, (_esbp)->esb_handle,\ + (_offset), (_edp)->ed_u32[0]); \ + \ + _NOTE(CONSTANTCONDITION) \ + if (_lock) \ + mtx_unlock(&((_esbp)->esb_lock)); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_BAR_WRITEQ(_esbp, _offset, _eqp) \ + do { \ + _NOTE(CONSTANTCONDITION) \ + KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_qword_t)), \ + ("not power of 2 aligned")); \ + \ + mtx_lock(&((_esbp)->esb_lock)); \ + \ + EFSYS_PROBE3(bar_writeq, unsigned int, (_offset), \ + uint32_t, (_eqp)->eq_u32[1], \ + uint32_t, (_eqp)->eq_u32[0]); \ + \ + bus_space_write_4((_esbp)->esb_tag, (_esbp)->esb_handle,\ + (_offset), (_eqp)->eq_u32[0]); \ + bus_space_write_4((_esbp)->esb_tag, (_esbp)->esb_handle,\ + (_offset+4), (_eqp)->eq_u32[1]); \ + \ + mtx_unlock(&((_esbp)->esb_lock)); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_BAR_WRITEO(_esbp, _offset, _eop, _lock) \ + do { \ + _NOTE(CONSTANTCONDITION) \ + KASSERT(IS_P2ALIGNED(_offset, sizeof (efx_oword_t)), \ + ("not power of 2 aligned")); \ + \ + _NOTE(CONSTANTCONDITION) \ + if (_lock) \ + mtx_lock(&((_esbp)->esb_lock)); \ + \ + EFSYS_PROBE5(bar_writeo, unsigned int, (_offset), \ + uint32_t, (_eop)->eo_u32[3], \ + uint32_t, (_eop)->eo_u32[2], \ + uint32_t, (_eop)->eo_u32[1], \ + uint32_t, (_eop)->eo_u32[0]); \ + \ + bus_space_write_4((_esbp)->esb_tag, (_esbp)->esb_handle,\ + (_offset), (_eop)->eo_u32[0]); \ + bus_space_write_4((_esbp)->esb_tag, (_esbp)->esb_handle,\ + (_offset+4), (_eop)->eo_u32[1]); \ + bus_space_write_4((_esbp)->esb_tag, (_esbp)->esb_handle,\ + (_offset+8), (_eop)->eo_u32[2]); \ + bus_space_write_4((_esbp)->esb_tag, (_esbp)->esb_handle,\ + (_offset+12), (_eop)->eo_u32[3]); \ + \ + _NOTE(CONSTANTCONDITION) \ + if (_lock) \ + mtx_unlock(&((_esbp)->esb_lock)); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +/* SPIN */ + +#define EFSYS_SPIN(_us) \ + do { \ + DELAY(_us); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_SLEEP EFSYS_SPIN + +/* BARRIERS */ + +/* Strict ordering guaranteed by devacc.devacc_attr_dataorder */ +#define EFSYS_MEM_READ_BARRIER() +#define EFSYS_PIO_WRITE_BARRIER() + +/* TIMESTAMP */ + +typedef clock_t efsys_timestamp_t; + +#define EFSYS_TIMESTAMP(_usp) \ + do { \ + clock_t now; \ + \ + now = ticks; \ + *(_usp) = now * hz / 1000000; \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +/* KMEM */ + +#define EFSYS_KMEM_ALLOC(_esip, _size, _p) \ + do { \ + (_esip) = (_esip); \ + (_p) = malloc((_size), M_SFXGE, M_WAITOK|M_ZERO); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_KMEM_FREE(_esip, _size, _p) \ + do { \ + (void) (_esip); \ + (void) (_size); \ + free((_p), M_SFXGE); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +/* LOCK */ + +typedef struct mtx efsys_lock_t; + +#define EFSYS_LOCK_MAGIC 0x000010c4 + +#define EFSYS_LOCK(_lockp, _state) \ + do { \ + mtx_lock(_lockp); \ + (_state) = EFSYS_LOCK_MAGIC; \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_UNLOCK(_lockp, _state) \ + do { \ + if ((_state) != EFSYS_LOCK_MAGIC) \ + KASSERT(B_FALSE, ("not locked")); \ + mtx_unlock(_lockp); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +/* PREEMPT */ + +#define EFSYS_PREEMPT_DISABLE(_state) \ + do { \ + (_state) = (_state); \ + critical_enter(); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_PREEMPT_ENABLE(_state) \ + do { \ + (_state) = (_state); \ + critical_exit(_state); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +/* STAT */ + +typedef uint64_t efsys_stat_t; + +#define EFSYS_STAT_INCR(_knp, _delta) \ + do { \ + *(_knp) += (_delta); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_STAT_DECR(_knp, _delta) \ + do { \ + *(_knp) -= (_delta); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_STAT_SET(_knp, _val) \ + do { \ + *(_knp) = (_val); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_STAT_SET_QWORD(_knp, _valp) \ + do { \ + *(_knp) = le64toh((_valp)->eq_u64[0]); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_STAT_SET_DWORD(_knp, _valp) \ + do { \ + *(_knp) = le32toh((_valp)->ed_u32[0]); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_STAT_INCR_QWORD(_knp, _valp) \ + do { \ + *(_knp) += le64toh((_valp)->eq_u64[0]); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +#define EFSYS_STAT_SUBR_QWORD(_knp, _valp) \ + do { \ + *(_knp) -= le64toh((_valp)->eq_u64[0]); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) + +/* ERR */ + +extern void sfxge_err(efsys_identifier_t *, unsigned int, + uint32_t, uint32_t); + +#if EFSYS_OPT_DECODE_INTR_FATAL +#define EFSYS_ERR(_esip, _code, _dword0, _dword1) \ + do { \ + sfxge_err((_esip), (_code), (_dword0), (_dword1)); \ + _NOTE(CONSTANTCONDITION) \ + } while (B_FALSE) +#endif + +/* ASSERT */ + +#define EFSYS_ASSERT(_exp) do { \ + if (!(_exp)) \ + panic(#_exp); \ + } while (0) + +#define EFSYS_ASSERT3(_x, _op, _y, _t) do { \ + const _t __x = (_t)(_x); \ + const _t __y = (_t)(_y); \ + if (!(__x _op __y)) \ + panic("assertion failed at %s:%u", __FILE__, __LINE__); \ + } while(0) + +#define EFSYS_ASSERT3U(_x, _op, _y) EFSYS_ASSERT3(_x, _op, _y, uint64_t) +#define EFSYS_ASSERT3S(_x, _op, _y) EFSYS_ASSERT3(_x, _op, _y, int64_t) +#define EFSYS_ASSERT3P(_x, _op, _y) EFSYS_ASSERT3(_x, _op, _y, uintptr_t) + +#ifdef __cplusplus +} +#endif + +#endif /* _SYS_EFSYS_H */ Added: head/sys/dev/sfxge/common/efx.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/dev/sfxge/common/efx.h Wed Nov 16 17:11:13 2011 (r227569) @@ -0,0 +1,1893 @@ +/*- + * Copyright 2006-2009 Solarflare Communications Inc. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _SYS_EFX_H +#define _SYS_EFX_H + +#include "efsys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define EFX_STATIC_ASSERT(_cond) ((void)sizeof(char[(_cond) ? 1 : -1])) + +#define EFX_ARRAY_SIZE(_array) (sizeof(_array) / sizeof((_array)[0])) + +#ifndef EFSYS_MEM_IS_NULL +#define EFSYS_MEM_IS_NULL(_esmp) ((_esmp)->esm_base == NULL) +#endif + +typedef enum efx_family_e { + EFX_FAMILY_INVALID, + EFX_FAMILY_FALCON, + EFX_FAMILY_SIENA, + EFX_FAMILY_NTYPES +} efx_family_t; + *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201111161711.pAGHBDkq058627>