Date: Thu, 4 Nov 2021 16:02:57 GMT From: Adrian Chadd <adrian@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: cfd06987029a - main - ipq4018: add qcom-gcc-ipq4018 and dependencies into the build Message-ID: <202111041602.1A4G2vMG003815@gitrepo.freebsd.org>
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The branch main has been updated by adrian: URL: https://cgit.FreeBSD.org/src/commit/?id=cfd06987029ac1bf5f6a6be2d87ade7358bd59ca commit cfd06987029ac1bf5f6a6be2d87ade7358bd59ca Author: Adrian Chadd <adrian@FreeBSD.org> AuthorDate: 2021-10-31 03:45:17 +0000 Commit: Adrian Chadd <adrian@FreeBSD.org> CommitDate: 2021-11-04 16:02:43 +0000 ipq4018: add qcom-gcc-ipq4018 and dependencies into the build * add the extres stuff into the build, I'm going to end up leveraging all of it * include the qcom-gcc-ipq4018 driver which currently implements the hwreset side of the API. Reviewed by: andrew, manu, imp Differential Revision: https://reviews.freebsd.org/D32723 --- sys/arm/conf/std.qca | 12 +++++ sys/arm/qualcomm/qcom_gcc_ipq4018_clock.c | 82 +++++++++++++++++++++++++++++++ sys/arm/qualcomm/std.ipq4018 | 1 + 3 files changed, 95 insertions(+) diff --git a/sys/arm/conf/std.qca b/sys/arm/conf/std.qca index 00d627b77b7b..09cd61078870 100644 --- a/sys/arm/conf/std.qca +++ b/sys/arm/conf/std.qca @@ -12,6 +12,15 @@ files "../qualcomm/std.ipq4018" device uart device uart_msm # Qualcomm MSM UART driver +# EXT_RESOURCES pseudo devices +options EXT_RESOURCES +device clk +device phy +device hwreset +device nvmem +device regulator +device syscon + # Random device qcom_rnd @@ -28,6 +37,9 @@ device mpcore_timer # PSCI - SMC calls, needed for qualcomm SCM device psci +# Clock/Reset provider +device qcom_gcc_ipq4018 + options FDT # Disable CP14 work in DDB as TZ won't let us by default diff --git a/sys/arm/qualcomm/qcom_gcc_ipq4018_clock.c b/sys/arm/qualcomm/qcom_gcc_ipq4018_clock.c new file mode 100644 index 000000000000..f7f7a6c348ba --- /dev/null +++ b/sys/arm/qualcomm/qcom_gcc_ipq4018_clock.c @@ -0,0 +1,82 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2021, Adrian Chadd <adrian@FreeBSD.org> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice unmodified, this list of conditions, and the following + * disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/* Driver for Qualcomm IPQ4018 clock and reset device */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/kernel.h> +#include <sys/malloc.h> +#include <sys/module.h> +#include <sys/sglist.h> +#include <sys/random.h> +#include <sys/stdatomic.h> +#include <sys/mutex.h> + +#include <machine/bus.h> +#include <machine/resource.h> +#include <sys/bus.h> + +#include <dev/fdt/fdt_common.h> +#include <dev/ofw/ofw_bus.h> +#include <dev/ofw/ofw_bus_subr.h> + +#include <dt-bindings/clock/qcom,gcc-ipq4019.h> + +#include <arm/qualcomm/qcom_gcc_ipq4018_var.h> + + +/* + * Fixed frequency clock sources: + * + * P_XO - 48MHz + * sleep-clk - is really 32KHz, although older DTS have it as 32.768KHz + */ + +/* + * PLL derived sources: + * + * P_FEPLL125 - 125MHz + * P_FEPLL125DLY - 125MHz + * P_FEPLL200 - 200MHz + * P_FEPLL500 - 500MHz + * P_FEPLLWCSS2G - TBD + * P_FEPLLWCSS5G - TBD + * + * Then there are two DDR PLLs which are treated/configured slightly + * differently: + * + * P_DDRPLLAPSS - TBD + * P_DDRPLLSDCC - TBD + */ + +/* + * Interesting stuff in Linux whilst I reverse engineer + figure it out: + * /sys/kernel/debug/clk + */ diff --git a/sys/arm/qualcomm/std.ipq4018 b/sys/arm/qualcomm/std.ipq4018 index 7e8ac39e7222..913314e92301 100644 --- a/sys/arm/qualcomm/std.ipq4018 +++ b/sys/arm/qualcomm/std.ipq4018 @@ -6,4 +6,5 @@ arm/qualcomm/qcom_cpu_kpssv2.c optional smp dev/qcom_rnd/qcom_rnd.c optional qcom_rnd arm/qualcomm/qcom_gcc_ipq4018.c optional qcom_gcc_ipq4018 arm/qualcomm/qcom_gcc_ipq4018_reset.c optional qcom_gcc_ipq4018 +arm/qualcomm/qcom_gcc_ipq4018_clock.c optional qcom_gcc_ipq4018
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