Date: Sun, 15 Mar 1998 21:51:21 +0100 (MET) From: Wolfgang Helbig <helbig@Informatik.BA-Stuttgart.DE> To: freebsd-isdn@FreeBSD.ORG Subject: Re: i4b-L1-F_ill:What is this? Message-ID: <199803152051.VAA00554@rvc1.informatik.ba-stuttgart.de> In-Reply-To: <199802241233.NAA00376@cat.turbocat.de> from David Wetzel at "Feb 24, 98 01:33:58 pm"
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Hi,
Now and then, depending on the configuration, the layer-1 finite
state machine seems to try an illegal state transition. This is
because the driver tries to mirror the FSM built into the ISAC
chip. If the FSM is switching to fast some intermediate transitions
might not be reported to the driver. The last transition then
makes the driver think something bad has happened.
This patch takes this into account. I surely hope this to be the
last change in i4b_l1fsm.c for a while.
If anyone sees something illegal in layer 1 *or* if you see a loop
of TEI-ID requests and timeouts after applying this patch please
report.
This diff is against i4b-00.50 from March 13th.
Wolfgang
--- /home/helbig/src/i4b/layer1/i4b_l1fsm.c Thu Mar 12 14:26:25 1998
+++ layer1/i4b_l1fsm.c Sun Mar 15 11:38:58 1998
@@ -412,11 +412,11 @@
/* EVENT: */
/* indications */
/* EV_PU */ {{F_PU1, ST_F4}, {F_PU2, ST_F4}, {F_PU2, ST_F3b}, {F_PU2, ST_F3b}, {F_PU2, ST_F3b}, {F_PU2, ST_F3b}, {F_PU2, ST_F3b}, {F_PU2, ST_F3b}, {F_ill, ST_ILL}},
-/* EV_DR */ {{F_ill, ST_ILL}, {F_ill, ST_ILL}, {F_ill, ST_ILL}, {F_ill, ST_ILL}, {F_DR, ST_F3c}, {F_DR, ST_F3c}, {F_DR, ST_F3c}, {F_DR, ST_F3c}, {F_ill, ST_ILL}},
-/* EV_RS */ {{F_RS1, ST_F5}, {F_RS1, ST_F5}, {F_RS1, ST_F5}, {F_RS1, ST_F5}, {F_ill, ST_ILL}, {F_RS2, ST_F8}, {F_RS2, ST_F8}, {F_NcNa, ST_F8}, {F_ill, ST_ILL}},
-/* EV_AR I2 */ {{F_ill, ST_ILL}, {F_ill, ST_ILL}, {F_ill, ST_ILL}, {F_ill, ST_ILL}, {F_ARD1, ST_F6}, {F_ill, ST_ILL}, {F_ARD2, ST_F6}, {F_ARD3, ST_F6}, {F_ill, ST_ILL}},
-/* EV_A8 I4 */ {{F_ill, ST_ILL}, {F_ill, ST_ILL}, {F_ill, ST_ILL}, {F_ill, ST_ILL}, {F_AI81, ST_F7}, {F_AI82, ST_F7}, {F_ill, ST_ILL}, {F_AI82, ST_F7}, {F_ill, ST_ILL}},
-/* EV_A1 I4 */ {{F_ill, ST_ILL}, {F_ill, ST_ILL}, {F_ill, ST_ILL}, {F_ill, ST_ILL}, {F_AI11, ST_F7}, {F_AI12, ST_F7}, {F_ill, ST_ILL}, {F_AI12, ST_F7}, {F_ill, ST_ILL}},
+/* EV_DR */ {{F_DR, ST_F3c}, {F_DR, ST_F3c}, {F_DR, ST_F3c}, {F_DR, ST_F3c}, {F_DR, ST_F3c}, {F_DR, ST_F3c}, {F_DR, ST_F3c}, {F_DR, ST_F3c}, {F_ill, ST_ILL}},
+/* EV_RS */ {{F_RS1, ST_F5}, {F_RS1, ST_F5}, {F_RS1, ST_F5}, {F_RS1, ST_F5}, {F_RS2, ST_F8}, {F_RS2, ST_F8}, {F_RS2, ST_F8}, {F_NcNa, ST_F8}, {F_ill, ST_ILL}},
+/* EV_AR I2 */ {{F_ARD1, ST_F6}, {F_ARD1, ST_F6}, {F_ARD1, ST_F6}, {F_ARD1, ST_F6}, {F_ARD1, ST_F6}, {F_ill, ST_ILL}, {F_ARD2, ST_F6}, {F_ARD3, ST_F6}, {F_ill, ST_ILL}},
+/* EV_A8 I4 */ {{F_AI81, ST_F7}, {F_AI81, ST_F7}, {F_AI81, ST_F7}, {F_AI81, ST_F7}, {F_AI81, ST_F7}, {F_AI82, ST_F7}, {F_ill, ST_ILL}, {F_AI82, ST_F7}, {F_ill, ST_ILL}},
+/* EV_A1 I4 */ {{F_AI11, ST_F7}, {F_AI11, ST_F7}, {F_AI11, ST_F7}, {F_AI11, ST_F7}, {F_AI11, ST_F7}, {F_AI12, ST_F7}, {F_ill, ST_ILL}, {F_AI12, ST_F7}, {F_ill, ST_ILL}},
/* EV_DI */ {{F_ill, ST_ILL}, {F_DID, ST_F3a}, {F_DID, ST_F3a}, {F_DID, ST_F3a}, {F_DID, ST_F3a}, {F_DID, ST_F3a}, {F_DID, ST_F3a}, {F_DID, ST_F3a}, {F_ill, ST_ILL}},
/* something else */
/* EV_T3 */ {{F_NcNa, ST_F3a}, {F_NcNa, ST_F3b}, {F_NcNa, ST_F3c}, {F_T3ex, ST_F3c}, {F_T3ex, ST_F3c}, {F_T3ex, ST_F3c}, {F_ill, ST_ILL}, {F_T3ex, ST_F3c}, {F_ill, ST_ILL}},
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