Date: Tue, 23 Jun 2020 17:17:13 +0000 (UTC) From: Mitchell Horne <mhorne@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r362546 - head/share/man/man7 Message-ID: <202006231717.05NHHD5B078834@repo.freebsd.org>
next in thread | raw e-mail | index | archive | help
Author: mhorne Date: Tue Jun 23 17:17:13 2020 New Revision: 362546 URL: https://svnweb.freebsd.org/changeset/base/362546 Log: arch(7): small corrections for RISC-V Document that RISC-V supports multiple page sizes: 4K, 2M, and 1G. RISC-V's long double is always 128-bits wide, therefore quad precision. Mention __riscv_float_abi_soft, which can be used to differentiate between riscv64 and riscv64sf in userland code. MFC after: 3 days Modified: head/share/man/man7/arch.7 Modified: head/share/man/man7/arch.7 ============================================================================== --- head/share/man/man7/arch.7 Tue Jun 23 16:43:48 2020 (r362545) +++ head/share/man/man7/arch.7 Tue Jun 23 17:17:13 2020 (r362546) @@ -26,7 +26,7 @@ .\" .\" $FreeBSD$ .\" -.Dd March 28, 2020 +.Dd June 23, 2020 .Dt ARCH 7 .Os .Sh NAME @@ -256,8 +256,8 @@ is 8 bytes on all supported architectures except i386. .It powerpc Ta 4K .It powerpcspe Ta 4K .It powerpc64 Ta 4K -.It riscv64 Ta 4K -.It riscv64sf Ta 4K +.It riscv64 Ta 4K, 2M, 1G +.It riscv64sf Ta 4K, 2M, 1G .El .Ss Floating Point .Bl -column -offset indent "Architecture" "float, double" "long double" @@ -279,8 +279,8 @@ is 8 bytes on all supported architectures except i386. .It powerpc Ta hard Ta hard, double precision .It powerpcspe Ta hard Ta hard, double precision .It powerpc64 Ta hard Ta hard, double precision -.It riscv64 Ta hard Ta hard, double precision -.It riscv64sf Ta soft Ta soft, double precision +.It riscv64 Ta hard Ta hard, quad precision +.It riscv64sf Ta soft Ta soft, quad precision .El .Ss Default Tool Chain .Fx @@ -358,7 +358,7 @@ Architecture-specific macros: .It powerpcspe Ta Dv __powerpc__, Dv __SPE__ .It powerpc64 Ta Dv __powerpc__, Dv __powerpc64__ .It riscv64 Ta Dv __riscv, Dv __riscv_xlen == 64 -.It riscv64sf Ta Dv __riscv, Dv __riscv_xlen == 64 +.It riscv64sf Ta Dv __riscv, Dv __riscv_xlen == 64, Dv __riscv_float_abi_soft .El .Pp Compilers may define additional variants of architecture-specific macros.
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?202006231717.05NHHD5B078834>