Date: Tue, 3 Mar 1998 14:56:31 -0800 (PST) From: Tor Egge <tegge@FreeBSD.ORG> To: cvs-committers@FreeBSD.ORG, cvs-all@FreeBSD.ORG, cvs-sys@FreeBSD.ORG Subject: cvs commit: src/sys/i386/i386 mp_apicdefs.s mp_machdep.c src/sys/i386/include smp.h smptests.h src/sys/i386/isa apic_ipl.s apic_vector.s ipl.s intr_machdep.c intr_machdep.h Message-ID: <199803032256.OAA09814@freefall.freebsd.org>
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tegge 1998/03/03 14:56:31 PST
Modified files:
sys/i386/i386 mp_apicdefs.s mp_machdep.c
sys/i386/include smp.h smptests.h
sys/i386/isa apic_ipl.s apic_vector.s ipl.s
intr_machdep.c intr_machdep.h
Log:
When entering the apic version of slow interrupt handler, level
interrupts are masked, and EOI is sent iff the corresponding ISR bit
is set in the local apic. If the CPU cannot obtain the interrupt
service lock (currently the global kernel lock) the interrupt is
forwarded to the CPU holding that lock.
Clock interrupts now have higher priority than other slow interrupts.
Revision Changes Path
1.3 +4 -3 src/sys/i386/i386/mp_apicdefs.s
1.69 +60 -1 src/sys/i386/i386/mp_machdep.c
1.38 +4 -1 src/sys/i386/include/smp.h
1.29 +32 -1 src/sys/i386/include/smptests.h
1.18 +4 -1 src/sys/i386/isa/apic_ipl.s
1.27 +303 -40 src/sys/i386/isa/apic_vector.s
1.20 +25 -1 src/sys/i386/isa/ipl.s
1.9 +26 -12 src/sys/i386/isa/intr_machdep.c
1.11 +5 -1 src/sys/i386/isa/intr_machdep.h
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