Date: Tue, 4 Oct 2011 11:22:13 -0400 From: Andrew Duane <aduane@juniper.net> To: Warner Losh <imp@bsdimp.com>, Adrian Chadd <adrian@freebsd.org> Cc: "Jayachandran C." <jchandra@freebsd.org>, Kostik Belousov <kostikbel@gmail.com>, Alexander Motin <mav@freebsd.org>, "freebsd-mips@freebsd.org" <freebsd-mips@freebsd.org> Subject: Re: svn commit: r225892 - head/sys/mips/mips Message-ID: <kor1ebmmdclae4u7bstwrc2c.1317741744919@email.android.com>
next in thread | raw e-mail | index | archive | help
Let me pull my MIPS manual when I get in. It exactly specifies the hazards = for each bit. Warner Losh <imp@bsdimp.com> wrote: On Oct 3, 2011, at 7:38 PM, Adrian Chadd wrote: > On 4 October 2011 07:09, Andrew Duane <aduane@juniper.net> wrote: >> The COP0_SYNC's should be there (should there also be one after the MTC0= in MipsKernIntr?). The ISA says a hazard is needed, so that should be refl= ected. I assume different platforms define COP0_SYNC for themselves as need= ed? > > Is one needed after the mtc0 after StartWaitSkip? I don't think it matters. The COP0_SYNC is needed when you want to flush t= he instruction pipeline so that changes to COP0 don't affect them 'randomly= '. However, in this case. Either we're setting a bit that's already set, = which won't change anything, or we're setting a bit that's clear, which wil= l just delay the delivery of the interrupt a few cycles. The race where it= happens before the wait instruction is handled by the rest of the patch. Warner
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?kor1ebmmdclae4u7bstwrc2c.1317741744919>