Date: Thu, 11 Jul 2013 16:23:02 GMT From: Brooks Davis <brooks@FreeBSD.org> To: Perforce Change Reviews <perforce@FreeBSD.org> Subject: PERFORCE change 231031 for review Message-ID: <201307111623.r6BGN2xZ043282@skunkworks.freebsd.org>
index | next in thread | raw e-mail
http://p4web.freebsd.org/@@231031?ac=10 Change 231031 by brooks@brooks_zenith on 2013/07/11 16:22:08 Turn the unused and uncompilable MIPS_DISABLE_L1_CACHE define in cache.c into an option and when set force I- and D-cache line sizes to 0 (the latter part might be better as a tunable). Fix some casts in an #if 0'd bit of code which attempts to disable L1 cache ops when the cache is coherent. Affected files ... .. //depot/projects/ctsrd/beribsd/src/sys/conf/options.mips#13 edit .. //depot/projects/ctsrd/beribsd/src/sys/mips/mips/cache.c#4 edit .. //depot/projects/ctsrd/beribsd/src/sys/mips/mips/cpu.c#5 edit Differences ... ==== //depot/projects/ctsrd/beribsd/src/sys/conf/options.mips#13 (text+ko) ==== @@ -69,6 +69,11 @@ MAXMEM opt_global.h # +# Manual override of cache config +# +MIPS_DISABLE_L1_CACHE opt_global.h + +# # Options that control the Cavium Simple Executive. # OCTEON_MODEL opt_cvmx.h ==== //depot/projects/ctsrd/beribsd/src/sys/mips/mips/cache.c#4 (text+ko) ==== @@ -116,11 +116,9 @@ #ifdef MIPS_DISABLE_L1_CACHE case 0: - mips_cache_ops.mco_icache_sync_all = cache_noop; - mips_cache_ops.mco_icache_sync_range = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_icache_sync_range_index = - (void (*)(vaddr_t, vsize_t))cache_noop; + mips_cache_ops.mco_icache_sync_all = (void (*)(void))cache_noop; + mips_cache_ops.mco_icache_sync_range = cache_noop; + mips_cache_ops.mco_icache_sync_range_index = cache_noop; break; #endif default: @@ -193,20 +191,16 @@ #endif #ifdef MIPS_DISABLE_L1_CACHE case 0: - mips_cache_ops.mco_pdcache_wbinv_all = cache_noop; - mips_cache_ops.mco_intern_pdcache_wbinv_all = cache_noop; - mips_cache_ops.mco_pdcache_wbinv_range = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_pdcache_wbinv_range_index = - (void (*)(vaddr_t, vsize_t))cache_noop; + mips_cache_ops.mco_pdcache_wbinv_all = + mips_cache_ops.mco_intern_pdcache_wbinv_all = + (void (*)(void))cache_noop; + mips_cache_ops.mco_pdcache_wbinv_range = cache_noop; + mips_cache_ops.mco_pdcache_wbinv_range_index = cache_noop; mips_cache_ops.mco_intern_pdcache_wbinv_range_index = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_pdcache_inv_range = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_pdcache_wb_range = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_intern_pdcache_wb_range = - (void (*)(vaddr_t, vsize_t))cache_noop; + cache_noop; + mips_cache_ops.mco_pdcache_inv_range = cache_noop; + mips_cache_ops.mco_pdcache_wb_range = cache_noop; + mips_cache_ops.mco_intern_pdcache_wb_range = cache_noop; break; #endif default: @@ -222,26 +216,22 @@ #ifdef CACHE_DEBUG printf(" Dcache is coherent\n"); #endif - mips_cache_ops.mco_pdcache_wbinv_all = cache_noop; - mips_cache_ops.mco_pdcache_wbinv_range = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_pdcache_wbinv_range_index = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_pdcache_inv_range = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_pdcache_wb_range = - (void (*)(vaddr_t, vsize_t))cache_noop; + mips_cache_ops.mco_pdcache_wbinv_all = + (void (*)(void))cache_noop; + mips_cache_ops.mco_pdcache_wbinv_range = cache_noop; + mips_cache_ops.mco_pdcache_wbinv_range_index = cache_noop; + mips_cache_ops.mco_pdcache_inv_range = cache_noop; + mips_cache_ops.mco_pdcache_wb_range = cache_noop; } if (mips_cpu_flags & CPU_MIPS_I_D_CACHE_COHERENT) { #ifdef CACHE_DEBUG printf(" Icache is coherent against Dcache\n"); #endif mips_cache_ops.mco_intern_pdcache_wbinv_all = + (void (*)(void))cache_noop; + mips_cache_ops.mco_intern_pdcache_wbinv_range_index = cache_noop; - mips_cache_ops.mco_intern_pdcache_wbinv_range_index = - (void (*)(vaddr_t, vsize_t))cache_noop; - mips_cache_ops.mco_intern_pdcache_wb_range = - (void (*)(vaddr_t, vsize_t))cache_noop; + mips_cache_ops.mco_intern_pdcache_wb_range = cache_noop; } #endif ==== //depot/projects/ctsrd/beribsd/src/sys/mips/mips/cpu.c#5 (text+ko) ==== @@ -128,6 +128,9 @@ #endif /* L1 instruction cache. */ +#ifdef MIPS_DISABLE_L1_CACHE + cpuinfo->l1.ic_linesize = 0; +#else tmp = (cfg1 & MIPS_CONFIG1_IL_MASK) >> MIPS_CONFIG1_IL_SHIFT; if (tmp != 0) { cpuinfo->l1.ic_linesize = 1 << (tmp + 1); @@ -135,9 +138,13 @@ cpuinfo->l1.ic_nsets = 1 << (((cfg1 & MIPS_CONFIG1_IS_MASK) >> MIPS_CONFIG1_IS_SHIFT) + 6); } +#endif + /* L1 data cache. */ +#ifdef MIPS_DISABLE_L1_CACHE + cpuinfo->l1.dc_linesize = 0; +#else #ifndef CPU_CNMIPS - /* L1 data cache. */ tmp = (cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT; if (tmp != 0) { cpuinfo->l1.dc_linesize = 1 << (tmp + 1); @@ -173,6 +180,7 @@ /* All Octeon models use 128 byte line size. */ cpuinfo->l1.dc_linesize = 128; #endif +#endif cpuinfo->l1.ic_size = cpuinfo->l1.ic_linesize * cpuinfo->l1.ic_nsets * cpuinfo->l1.ic_nways;help
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201307111623.r6BGN2xZ043282>