Date: Thu, 29 Oct 2009 13:28:37 +0000 (UTC) From: Nathan Whitehorn <nwhitehorn@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r198583 - head/sys/dev/ata/chipsets Message-ID: <200910291328.n9TDSbUC097569@svn.freebsd.org>
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Author: nwhitehorn Date: Thu Oct 29 13:28:37 2009 New Revision: 198583 URL: http://svn.freebsd.org/changeset/base/198583 Log: Add some magic taken from OS X and Linux to support early revision K2 SATA controllers, like those found on the G5 Xserve. Reviewed by: mav Modified: head/sys/dev/ata/chipsets/ata-serverworks.c Modified: head/sys/dev/ata/chipsets/ata-serverworks.c ============================================================================== --- head/sys/dev/ata/chipsets/ata-serverworks.c Thu Oct 29 13:27:14 2009 (r198582) +++ head/sys/dev/ata/chipsets/ata-serverworks.c Thu Oct 29 13:28:37 2009 (r198583) @@ -41,6 +41,9 @@ __FBSDID("$FreeBSD$"); #include <sys/sema.h> #include <sys/taskqueue.h> #include <vm/uma.h> +#ifdef __powerpc__ +#include <machine/intr_machdep.h> +#endif #include <machine/stdarg.h> #include <machine/resource.h> #include <machine/bus.h> @@ -106,6 +109,13 @@ static int ata_serverworks_status(device_t dev) { struct ata_channel *ch = device_get_softc(dev); + struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); + + /* + * Check if this interrupt belongs to our channel. + */ + if (!(ATA_INL(ctlr->r_res2, 0x1f80) & (1 << ch->unit))) + return (0); /* * We need to do a 4-byte read on the status reg before the values @@ -208,8 +218,29 @@ ata_serverworks_ch_attach(device_t dev) ch->hw.tf_write = ata_serverworks_tf_write; #ifdef __powerpc__ ch->hw.status = ata_serverworks_status; + + /* Make sure that our interrupt is edge triggered */ + powerpc_config_intr(bus_get_resource_start(device_get_parent(dev), + SYS_RES_IRQ, 0), INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH); #endif + if (ctlr->chip->chipid == ATA_K2) { + /* + * The revision 1 K2 SATA controller has interesting bugs. Patch them. + * These magic numbers regulate interrupt delivery in the first few + * cases and are pure magic in the last case. + * + * Values obtained from the Darwin driver. + */ + + ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, 0x04); + ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff); + ATA_IDX_OUTL(ch, ATA_SCONTROL, 0x00000300); + ATA_OUTL(ctlr->r_res2, ch_offset + 0x88, 0); + ATA_OUTL(ctlr->r_res2, ch_offset + 0x80, + ATA_INL(ctlr->r_res2, ch_offset + 0x80) & ~0x00040000); + } + /* chip does not reliably do 64K DMA transfers */ ch->dma.max_iosize = 64 * DEV_BSIZE;
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