Date: Thu, 16 Aug 2001 18:13:10 -0600 From: "Brad Morgan" <B-Morgan@concentric.net> To: "Paul" <tribble@tribble.net> Cc: <stable@FreeBSD.ORG> Subject: RE: New kernel option CPU_ENABLE_SSE Message-ID: <NABBJOOEOFODEALNMJAJMENEEEAA.B-Morgan@concentric.net> In-Reply-To: <20010816170035.A45250@tribble.net>
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Correct me if I'm wrong but I would suspect that kernel support for MMX, SSE, SSE2, etc. means at a minimum that any state generated by this set of instructions needs to be saved across context switches. Otherwise, two or more processes using those instructions at the same time might tend to get each other confused. -----Original Message----- From: owner-freebsd-stable@FreeBSD.ORG [mailto:owner-freebsd-stable@FreeBSD.ORG]On Behalf Of Paul Sent: Thursday, August 16, 2001 5:01 PM To: Kris Kennaway Cc: stable@FreeBSD.ORG Subject: Re: New kernel option CPU_ENABLE_SSE Once upon a time, Kris Kennaway <kris@obsecurity.org> scribed: > On Thu, Aug 16, 2001 at 06:00:40PM -0400, Kenneth W Cochran wrote: > > Am I correct in assuming that "older generation" 686 CPUs > > (i.e. pre-Pentium-III) don't support SSE & that SSE is a > > function/enhancement of "newer generation" CPUs? > > Yes. I think it came in with the Pentium III. Correct. Pentium III supports SSE, as well do the newer Celeron chips which are essentially PIIIs with less L2 cache. That's my understanding, anyhow. Don't know anything about SSE2. Considering how worthless PIVs are, really, does it matter? :P > Kris Regards, Paul <tribble@tribble.net> http://www.tribble.net/ Bush - not popularly elected, making unpopular decisions against the will of the people. If you're not outraged, I guess you aren't paying attention. To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-stable" in the body of the message To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-stable" in the body of the message
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