Date: Mon, 12 Jan 2026 07:56:01 +0000 From: Warner Losh <imp@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Cc: Minsoo Choo <minsoochoo0122@proton.me> Subject: git: c5dc38bcc291 - main - Remove all code under __SPE__ Message-ID: <6964a911.3ff1b.26f0fd13@gitrepo.freebsd.org>
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The branch main has been updated by imp: URL: https://cgit.FreeBSD.org/src/commit/?id=c5dc38bcc2916018566b3b6eb46bcbbc68adf01f commit c5dc38bcc2916018566b3b6eb46bcbbc68adf01f Author: Minsoo Choo <minsoochoo0122@proton.me> AuthorDate: 2026-01-10 04:32:35 +0000 Commit: Warner Losh <imp@FreeBSD.org> CommitDate: 2026-01-12 07:51:05 +0000 Remove all code under __SPE__ Signed-off-by: Minsoo Choo <minsoochoo0122@proton.me> Reviewed by: imp Pull Request: https://github.com/freebsd/freebsd-src/pull/1957 --- lib/msun/powerpc/fenv.c | 34 ------------- lib/msun/powerpc/fenv.h | 23 --------- libexec/rtld-elf/powerpc/rtld_start.S | 96 ----------------------------------- sys/powerpc/booke/booke_machdep.c | 8 --- sys/powerpc/booke/trap_subr.S | 22 -------- sys/powerpc/include/ieeefp.h | 8 --- sys/powerpc/powerpc/exec_machdep.c | 18 ------- sys/powerpc/powerpc/fpu.c | 3 -- sys/powerpc/powerpc/ptrace_machdep.c | 4 -- sys/powerpc/powerpc/swtch32.S | 12 ----- sys/powerpc/powerpc/trap.c | 36 ------------- usr.bin/gcore/elfcore.c | 2 - 12 files changed, 266 deletions(-) diff --git a/lib/msun/powerpc/fenv.c b/lib/msun/powerpc/fenv.c index da11d27a649f..cc0b518bb7c4 100644 --- a/lib/msun/powerpc/fenv.c +++ b/lib/msun/powerpc/fenv.c @@ -28,27 +28,17 @@ #define __fenv_static #include "fenv.h" -#ifdef __SPE__ -#include <sys/types.h> -#include <machine/spr.h> -#endif #ifdef __GNUC_GNU_INLINE__ #error "This file must be compiled with C99 'inline' semantics" #endif -#ifdef __SPE__ -const fenv_t __fe_dfl_env = SPEFSCR_DFLT; -#else const fenv_t __fe_dfl_env = 0x00000000; -#endif extern inline int feclearexcept(int __excepts); extern inline int fegetexceptflag(fexcept_t *__flagp, int __excepts); extern inline int fesetexceptflag(const fexcept_t *__flagp, int __excepts); -#ifndef __SPE__ extern inline int feraiseexcept(int __excepts); -#endif extern inline int fetestexcept(int __excepts); extern inline int fegetround(void); extern inline int fesetround(int __round); @@ -58,27 +48,3 @@ extern inline int fesetenv(const fenv_t *__envp); extern inline int feupdateenv(const fenv_t *__envp); extern inline int feenableexcept(int __mask); extern inline int fedisableexcept(int __mask); - -#ifdef __SPE__ -#define PMAX 0x7f7fffff -#define PMIN 0x00800000 -int feraiseexcept(int __excepts) -{ - uint32_t spefscr; - - spefscr = mfspr(SPR_SPEFSCR); - mtspr(SPR_SPEFSCR, spefscr | (__excepts & FE_ALL_EXCEPT)); - - if (__excepts & FE_INVALID) - __asm __volatile ("efsdiv %0, %0, %1" :: "r"(0), "r"(0)); - if (__excepts & FE_DIVBYZERO) - __asm __volatile ("efsdiv %0, %0, %1" :: "r"(1.0f), "r"(0)); - if (__excepts & FE_UNDERFLOW) - __asm __volatile ("efsmul %0, %0, %0" :: "r"(PMIN)); - if (__excepts & FE_OVERFLOW) - __asm __volatile ("efsadd %0, %0, %0" :: "r"(PMAX)); - if (__excepts & FE_INEXACT) - __asm __volatile ("efssub %0, %0, %1" :: "r"(PMIN), "r"(1.0f)); - return (0); -} -#endif diff --git a/lib/msun/powerpc/fenv.h b/lib/msun/powerpc/fenv.h index 49fffb196206..09fd4caafb43 100644 --- a/lib/msun/powerpc/fenv.h +++ b/lib/msun/powerpc/fenv.h @@ -40,17 +40,6 @@ typedef __uint32_t fenv_t; typedef __uint32_t fexcept_t; /* Exception flags */ -#ifdef __SPE__ -#define FE_OVERFLOW 0x00000100 -#define FE_UNDERFLOW 0x00000200 -#define FE_DIVBYZERO 0x00000400 -#define FE_INVALID 0x00000800 -#define FE_INEXACT 0x00001000 - -#define FE_ALL_INVALID FE_INVALID - -#define _FPUSW_SHIFT 6 -#else #define FE_INEXACT 0x02000000 #define FE_DIVBYZERO 0x04000000 #define FE_UNDERFLOW 0x08000000 @@ -78,7 +67,6 @@ typedef __uint32_t fexcept_t; FE_VXSNAN | FE_INVALID) #define _FPUSW_SHIFT 22 -#endif #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW) @@ -101,17 +89,10 @@ extern const fenv_t __fe_dfl_env; FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT) #ifndef _SOFT_FLOAT -#ifdef __SPE__ -#define __mffs(__env) \ - __asm __volatile("mfspr %0, 512" : "=r" ((__env)->__bits.__reg)) -#define __mtfsf(__env) \ - __asm __volatile("mtspr 512,%0;isync" :: "r" ((__env).__bits.__reg)) -#else #define __mffs(__env) \ __asm __volatile("mffs %0" : "=f" ((__env)->__d)) #define __mtfsf(__env) \ __asm __volatile("mtfsf 255,%0" :: "f" ((__env).__d)) -#endif #else #define __mffs(__env) #define __mtfsf(__env) @@ -167,9 +148,6 @@ fesetexceptflag(const fexcept_t *__flagp, int __excepts) return (0); } -#ifdef __SPE__ -extern int feraiseexcept(int __excepts); -#else __fenv_static inline int feraiseexcept(int __excepts) { @@ -182,7 +160,6 @@ feraiseexcept(int __excepts) __mtfsf(__r); return (0); } -#endif __fenv_static inline int fetestexcept(int __excepts) diff --git a/libexec/rtld-elf/powerpc/rtld_start.S b/libexec/rtld-elf/powerpc/rtld_start.S index e34cc56fc40c..d36649caa9be 100644 --- a/libexec/rtld-elf/powerpc/rtld_start.S +++ b/libexec/rtld-elf/powerpc/rtld_start.S @@ -101,17 +101,10 @@ _ENTRY(.rtld_start) sc _END(.rtld_start) -#ifdef __SPE__ -/* stack space for 30 GPRs + SPEFSCR/ACC/lr/cr */ -#define NREGS 31 -#define GPRWIDTH 8 -#define FUDGE 4 /* Fudge factor for alignment */ -#else /* stack space for 30 GPRs + lr/cr */ #define NREGS 30 #define GPRWIDTH 4 #define FUDGE 4 -#endif /* Stack frame needs the 12-byte ABI frame plus fudge factor. */ #define STACK_SIZE (NREGS * GPRWIDTH + 4 * 2 + 12 + FUDGE) @@ -125,11 +118,7 @@ _END(.rtld_start) */ _ENTRY(_rtld_bind_secureplt_start) stwu %r1,-STACK_SIZE(%r1) -#ifdef __SPE__ - evstdd %r0,24(%r1) -#else stw %r0,20(%r1) # save r0 -#endif /* * Instead of division which is costly we will use multiplicative @@ -157,110 +146,25 @@ _END(_rtld_bind_secureplt_start) _ENTRY(_rtld_bind_start) stwu %r1,-STACK_SIZE(%r1) -#ifdef __SPE__ - evstdd %r0,24(%r1) -#else stw %r0,20(%r1) # save r0 -#endif 1: mflr %r0 stw %r0,16(%r1) # save lr mfcr %r0 stw %r0,12(%r1) # save cr -#ifdef __SPE__ - evstdd %r3, 32(%r1) - evstdd %r4, 40(%r1) - evstdd %r5, 48(%r1) - evstdd %r6, 56(%r1) - evstdd %r7, 64(%r1) - evstdd %r8, 72(%r1) - evstdd %r9, 80(%r1) - evstdd %r10, 88(%r1) - evstdd %r11, 96(%r1) - evstdd %r12, 104(%r1) - evstdd %r13, 112(%r1) - evstdd %r14, 120(%r1) - evstdd %r15, 128(%r1) - evstdd %r16, 136(%r1) - evstdd %r17, 144(%r1) - evstdd %r18, 152(%r1) - evstdd %r19, 160(%r1) - evstdd %r20, 168(%r1) - evstdd %r21, 176(%r1) - evstdd %r22, 184(%r1) - evstdd %r23, 192(%r1) - evstdd %r24, 200(%r1) - evstdd %r25, 208(%r1) - evstdd %r26, 216(%r1) - evstdd %r27, 224(%r1) - evstdd %r28, 232(%r1) - evstdd %r29, 240(%r1) - evstdd %r30, 248(%r1) - li %r3, 256 - evstddx %r31, %r1, %r3 - evxor %r0, %r0, %r0 - li %r3, 264 - evmwumiaa %r0, %r0, %r0 - evstddx %r0, %r1, %r3 - mfspr %r3, SPR_SPEFSCR - stw %r3, 20(%r1) -#else stmw %r3,24(%r1) # save r3-r31 -#endif mr %r3,%r12 # obj mulli %r4,%r11,12 # rela index * sizeof(Elf_Rela) bl _rtld_bind # target addr = _rtld_bind(obj, reloff) mtctr %r3 # move absolute target addr into ctr -#ifdef __SPE__ - lwz %r3, 20(%r1) - mtspr SPR_SPEFSCR, %r3 - li %r3, 264 - evlddx %r0, %r3, %r1 - evmra %r0, %r0 - evldd %r3, 32(%r1) - evldd %r4, 40(%r1) - evldd %r5, 48(%r1) - evldd %r6, 56(%r1) - evldd %r7, 64(%r1) - evldd %r8, 72(%r1) - evldd %r9, 80(%r1) - evldd %r10, 88(%r1) - evldd %r11, 96(%r1) - evldd %r12, 104(%r1) - evldd %r13, 112(%r1) - evldd %r14, 120(%r1) - evldd %r15, 128(%r1) - evldd %r16, 136(%r1) - evldd %r17, 144(%r1) - evldd %r18, 152(%r1) - evldd %r19, 160(%r1) - evldd %r20, 168(%r1) - evldd %r21, 176(%r1) - evldd %r22, 184(%r1) - evldd %r23, 192(%r1) - evldd %r24, 200(%r1) - evldd %r25, 208(%r1) - evldd %r26, 216(%r1) - evldd %r27, 224(%r1) - evldd %r28, 232(%r1) - evldd %r29, 240(%r1) - evldd %r30, 248(%r1) - li %r0, 256 - evlddx %r31, %r1, %r0 -#else lmw %r3,24(%r1) # restore r3-r31 -#endif lwz %r0,12(%r1) # restore cr mtcr %r0 lwz %r0,16(%r1) # restore lr mtlr %r0 -#ifdef __SPE__ - evldd %r0,24(%r1) -#else lwz %r0,20(%r1) # restore r0 -#endif addi %r1,%r1,STACK_SIZE # restore stack bctr # jump to target diff --git a/sys/powerpc/booke/booke_machdep.c b/sys/powerpc/booke/booke_machdep.c index 1a37959b439f..467eb2ab9638 100644 --- a/sys/powerpc/booke/booke_machdep.c +++ b/sys/powerpc/booke/booke_machdep.c @@ -187,10 +187,6 @@ extern void *int_debug; extern void *int_debug_ed; extern void *int_vec; extern void *int_vecast; -#ifdef __SPE__ -extern void *int_spe_fpdata; -extern void *int_spe_fpround; -#endif #ifdef HWPMC_HOOKS extern void *int_performance_counter; #endif @@ -278,10 +274,6 @@ ivor_setup(void) case FSL_E500v1: case FSL_E500v2: SET_TRAP(SPR_IVOR32, int_vec); -#ifdef __SPE__ - SET_TRAP(SPR_IVOR33, int_spe_fpdata); - SET_TRAP(SPR_IVOR34, int_spe_fpround); -#endif break; } diff --git a/sys/powerpc/booke/trap_subr.S b/sys/powerpc/booke/trap_subr.S index 523d8b57d3bc..789e746dba3e 100644 --- a/sys/powerpc/booke/trap_subr.S +++ b/sys/powerpc/booke/trap_subr.S @@ -636,28 +636,6 @@ INTERRUPT(int_vecast) b trap_common -#ifdef __SPE__ -/***************************************************************************** - * Floating point Assist interrupt - ****************************************************************************/ -INTERRUPT(int_spe_fpdata) - STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) - FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_SPFPD) - addi %r3, %r1, CALLSIZE - bl spe_handle_fpdata - FRAME_LEAVE(SPR_SRR0, SPR_SRR1) - rfi - -INTERRUPT(int_spe_fpround) - STANDARD_PROLOG(SPR_SPRG1, PC_TEMPSAVE, SPR_SRR0, SPR_SRR1) - FRAME_SETUP(SPR_SPRG1, PC_TEMPSAVE, EXC_SPFPR) - addi %r3, %r1, CALLSIZE - bl spe_handle_fpround - FRAME_LEAVE(SPR_SRR0, SPR_SRR1) - rfi -#endif - - #ifdef HWPMC_HOOKS /***************************************************************************** * PMC Interrupt diff --git a/sys/powerpc/include/ieeefp.h b/sys/powerpc/include/ieeefp.h index 3aa92ff4522b..829e167aefae 100644 --- a/sys/powerpc/include/ieeefp.h +++ b/sys/powerpc/include/ieeefp.h @@ -10,19 +10,11 @@ /* Deprecated historical FPU control interface */ typedef int fp_except_t; -#ifdef __SPE__ -#define FP_X_OFL 0x01 /* overflow exception */ -#define FP_X_UFL 0x02 /* underflow exception */ -#define FP_X_DZ 0x04 /* divide-by-zero exception */ -#define FP_X_INV 0x08 /* invalid operation exception */ -#define FP_X_IMP 0x10 /* imprecise (loss of precision) */ -#else #define FP_X_IMP 0x01 /* imprecise (loss of precision) */ #define FP_X_DZ 0x02 /* divide-by-zero exception */ #define FP_X_UFL 0x04 /* underflow exception */ #define FP_X_OFL 0x08 /* overflow exception */ #define FP_X_INV 0x10 /* invalid operation exception */ -#endif typedef enum { FP_RN=0, /* round to nearest representable number */ diff --git a/sys/powerpc/powerpc/exec_machdep.c b/sys/powerpc/powerpc/exec_machdep.c index 8a33d0f589a7..18c9bddb84c5 100644 --- a/sys/powerpc/powerpc/exec_machdep.c +++ b/sys/powerpc/powerpc/exec_machdep.c @@ -646,18 +646,6 @@ cpu_update_pcb(struct thread *td) pcb->pcb_dscr = mfspr(SPR_DSCRP); #endif -#if defined(__SPE__) - /* - * On E500v2, single-precision scalar instructions and access to - * SPEFSCR may be used without PSL_VEC turned on, as long as they - * limit themselves to the low word of the registers. - * - * As such, we need to unconditionally save SPEFSCR, even though - * it is also updated in save_vec_nodrop(). - */ - pcb->pcb_vec.vscr = mfspr(SPR_SPEFSCR); -#endif - if (pcb_flags & PCB_FPU) save_fpu_nodrop(td); @@ -1155,9 +1143,6 @@ cpu_copy_thread(struct thread *td, struct thread *td0) pcb2->pcb_context[0] = pcb2->pcb_lr; #endif pcb2->pcb_cpu.aim.usr_vsid = 0; -#ifdef __SPE__ - pcb2->pcb_vec.vscr = SPEFSCR_DFLT; -#endif /* Setup to release spin count in fork_exit(). */ td->td_md.md_spinlock_count = 1; @@ -1215,9 +1200,6 @@ cpu_set_upcall(struct thread *td, void (*entry)(void *), void *arg, } td->td_pcb->pcb_flags = 0; -#ifdef __SPE__ - td->td_pcb->pcb_vec.vscr = SPEFSCR_DFLT; -#endif td->td_retval[0] = (register_t)entry; td->td_retval[1] = 0; diff --git a/sys/powerpc/powerpc/fpu.c b/sys/powerpc/powerpc/fpu.c index cc8f22f7dda3..3e43656874a7 100644 --- a/sys/powerpc/powerpc/fpu.c +++ b/sys/powerpc/powerpc/fpu.c @@ -317,7 +317,6 @@ disable_fpu(struct thread *td) pcb->pcb_flags &= ~(PCB_FPU | PCB_VSX); } -#ifndef __SPE__ /* * XXX: Implement fpu_kern_alloc_ctx/fpu_kern_free_ctx once fpu_kern_enter and * fpu_kern_leave can handle !FPU_KERN_NOCTX. @@ -403,5 +402,3 @@ is_fpu_kern_thread(u_int flags __unused) curpcb = curthread->td_pcb; return ((curpcb->pcb_flags & PCB_KERN_FPU) != 0); } - -#endif /* !__SPE__ */ diff --git a/sys/powerpc/powerpc/ptrace_machdep.c b/sys/powerpc/powerpc/ptrace_machdep.c index 619faabf3ce0..1b6afdf3c015 100644 --- a/sys/powerpc/powerpc/ptrace_machdep.c +++ b/sys/powerpc/powerpc/ptrace_machdep.c @@ -37,11 +37,7 @@ #include <machine/md_var.h> #include <machine/pcb.h> -#ifdef __SPE__ -#define PPC_FEATURE_VECTOR PPC_FEATURE_HAS_SPE -#else #define PPC_FEATURE_VECTOR PPC_FEATURE_HAS_ALTIVEC -#endif int cpu_ptrace(struct thread *td, int req, void *addr, int data) diff --git a/sys/powerpc/powerpc/swtch32.S b/sys/powerpc/powerpc/swtch32.S index ef1a397bf74d..7fc0641722aa 100644 --- a/sys/powerpc/powerpc/swtch32.S +++ b/sys/powerpc/powerpc/swtch32.S @@ -119,10 +119,6 @@ ENTRY(cpu_switch) bl save_vec .L2: -#if defined(__SPE__) - mfspr %r3,SPR_SPEFSCR - stw %r3,PCB_VSCR(%r17) -#endif mr %r3,%r14 /* restore old thread ptr */ bl pmap_deactivate /* Deactivate the current pmap */ @@ -176,10 +172,6 @@ blocked_loop: bl enable_vec .L4: -#if defined(__SPE__) - lwz %r3,PCB_VSCR(%r17) - mtspr SPR_SPEFSCR,%r3 -#endif /* thread to restore is in r3 */ mr %r3,%r17 /* Recover PCB ptr */ lmw %r12,PCB_CONTEXT(%r3) /* Load the non-volatile GP regs */ @@ -224,9 +216,5 @@ ENTRY(fork_trampoline) trapframe to simulate FRAME_SETUP does when allocating space for a frame pointer/saved LR */ -#ifdef __SPE__ - li %r3,SPEFSCR_DFLT - mtspr SPR_SPEFSCR, %r3 -#endif b trapexit END(fork_trampoline) diff --git a/sys/powerpc/powerpc/trap.c b/sys/powerpc/powerpc/trap.c index 203d270a504b..6843ce49b48f 100644 --- a/sys/powerpc/powerpc/trap.c +++ b/sys/powerpc/powerpc/trap.c @@ -861,41 +861,6 @@ fix_unaligned(struct thread *td, struct trapframe *frame) int indicator, reg; double *fpr; -#ifdef __SPE__ - indicator = (frame->cpu.booke.esr & (ESR_ST|ESR_SPE)); - if (indicator & ESR_SPE) { - if (copyin((void *)frame->srr0, &inst, sizeof(inst)) != 0) - return (-1); - reg = EXC_ALI_INST_RST(inst); - fpr = (double *)td->td_pcb->pcb_vec.vr[reg]; - fputhread = PCPU_GET(vecthread); - - /* Juggle the SPE to ensure that we've initialized - * the registers, and that their current state is in - * the PCB. - */ - if (fputhread != td) { - if (fputhread) - save_vec(fputhread); - enable_vec(td); - } - save_vec(td); - - if (!(indicator & ESR_ST)) { - if (copyin((void *)frame->dar, fpr, - sizeof(double)) != 0) - return (-1); - frame->fixreg[reg] = td->td_pcb->pcb_vec.vr[reg][1]; - enable_vec(td); - } else { - td->td_pcb->pcb_vec.vr[reg][1] = frame->fixreg[reg]; - if (copyout(fpr, (void *)frame->dar, - sizeof(double)) != 0) - return (-1); - } - return (0); - } -#else #ifdef BOOKE indicator = (frame->cpu.booke.esr & ESR_ST) ? EXC_ALI_STFD : EXC_ALI_LFD; #else @@ -939,7 +904,6 @@ fix_unaligned(struct thread *td, struct trapframe *frame) return (0); break; } -#endif return (-1); } diff --git a/usr.bin/gcore/elfcore.c b/usr.bin/gcore/elfcore.c index 86613a91ca73..3e6722225b36 100644 --- a/usr.bin/gcore/elfcore.c +++ b/usr.bin/gcore/elfcore.c @@ -372,9 +372,7 @@ elf_putnotes(pid_t pid, struct sbuf *sb, size_t *sizep) #endif #if defined(__powerpc__) elf_putnote(NT_PPC_VMX, elf_note_powerpc_vmx, tids + i, sb); -#ifndef __SPE__ elf_putnote(NT_PPC_VSX, elf_note_powerpc_vsx, tids + i, sb); -#endif #endif }home | help
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