Date: Tue, 14 Apr 2009 08:42:46 +0200 From: Marko Zec <zec@freebsd.org> To: freebsd-arch@freebsd.org Subject: Re: Simple #define for cache line size Message-ID: <200904140842.46501.zec@freebsd.org> In-Reply-To: <gs0984$i3i$1@ger.gmane.org> References: <alpine.BSF.2.00.0904111700241.19879@fledge.watson.org> <gs0984$i3i$1@ger.gmane.org>
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On Monday 13 April 2009 23:01:23 Ivan Voras wrote: > Robert Watson wrote: > > --- i386/include/param.h (revision 190941) > > +++ i386/include/param.h (working copy) > > @@ -74,6 +74,10 @@ > > #define ALIGNBYTES _ALIGNBYTES > > #define ALIGN(p) _ALIGN(p) > > > > +#ifndef CACHE_LINE_SIZE > > +#define CACHE_LINE_SIZE 64 > > +#endif > > Wouldn't it be better to continue the > > cpu I486_CPU > cpu I586_CPU > cpu I686_CPU > > series of defines in kernel configuration and define alignment per > CPU architecture? We would have to extend our notion of "CPU architecture" for that to make sense. For example, Pentium Pro / II CPUs had cache line size of 32 bytes, Intel Netburst CPUs (all Pentium-4 and Xeons of the time) have / had 128 bytes, while Pentium-III, Pentium-M and later Core CPUs have 64 bytes. They are all I686_CPU in our view. Marko > I guess it depends on the trends - are cache lines > expected to change in the near future? :)
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