Date: Wed, 20 Nov 1996 00:17 EST From: Barney Wolff <barney@databus.com> To: freebsd-smp@freebsd.org Subject: Re: 8259 vs APIC Message-ID: <329296a60.1bae@databus.databus.com>
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> From: Steve Passe <smp@csn.net> > Date: Tue, 19 Nov 1996 21:59:04 -0700 > > The 8259 ICU latches an INT that occurs while that INT is masked. > The IO APIC looses any INT occuring while that INT is masked. > Intel calls this a "design consideration", I call it "brain damage". If you'll pardon the naive opinion, it sounds to me as tho the 8259 is expecting to handle edge-triggered interrupts (as we know to be true, right?) but the APIC is really expecting level-triggered ints, where the int will still be there when it's finally unmasked. If that's true, I would be looking at a solution that kept the edge- triggered ints on the 8259, as nothing will save you otherwise. So what if you cut the rate of lost ints to one a week - that's utterly unacceptable for a production machine. I seem to recall that the APIC can be set for either edge or level, or am I just fantasizing again? Anyway, thanks for helping me understand the project better! Barney Wolff <barney@databus.com>
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