Date: Thu, 13 Dec 2001 19:40:20 +0100 (CET) From: =?ISO-8859-1?Q?G=E9rard_Roudier?= <groudier@free.fr> To: "Justin T. Gibbs" <gibbs@scsiguy.com> Cc: Greg Johnson <gjohnson@research.canon.com.au>, <freebsd-hackers@FreeBSD.ORG> Subject: Re: Bus master DMA problems Message-ID: <20011213193136.P2307-100000@gerard> In-Reply-To: <200112132012.fBDKCSg09049@aslan.scsiguy.com>
index | next in thread | previous in thread | raw e-mail
On Thu, 13 Dec 2001, Justin T. Gibbs wrote: > > > >There are a couple of rules in PCI you must have in mind when > >synchronization between PCI devices is needed. > > > >1) Interrupts are not synchronization events. They just send attention to > > the device driver (acts as SIGIO, for example). Some bridge may flush > > posted buffers on interrupt, but since interrupt can be shared, you > > must not rely on such mechanism. > > The exception to this rule are Message Signaled Interrupts. The interrupt > is asserted by DMAing a token into a mailbox in the chipset. Since posted > writes must complete in order, this mechanism guarantees that the interrupt > is only asserted once any previous writes have completed. MSI is part > of the PCI 2.2 spec, but may only start to be supported in upcoming PCI-X > chipsets. I don't know when FreeBSD will gain support for MSI. I didn't hear about this being actually implemented. Anyway, in the situation of the PCI device not stopping operations after signaling interrupts (as, for example, in sym that has hardware phase mismatch really supported for years or ahc), the flushing does not look this useful. Gérard. To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-hackers" in the body of the messagehelp
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?20011213193136.P2307-100000>