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Date:      Mon, 18 Jan 2010 11:40:39 -0800
From:      Pyun YongHyeon <pyunyh@gmail.com>
To:        Charles Owens <cowens@greatbaysoftware.com>
Cc:        freebsd-net@freebsd.org, davidch@FreeBSD.org
Subject:   Re: "PHY read timeout" with bce2 & 3 on FreeBSD 8.0
Message-ID:  <20100118194039.GA1336@michelle.cdnetworks.com>
In-Reply-To: <4B548107.5050603@greatbaysoftware.com>
References:  <4B548107.5050603@greatbaysoftware.com>

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On Mon, Jan 18, 2010 at 10:40:55AM -0500, Charles Owens wrote:
> Hello,
> 
> I'm working with a system (IBM System x3550 M2) that has four onboard
> bce(4) NICs.  Using FreeBSD 8.0, the first two seem to function fine,
> but the second two do not, yielding messages like this when a cable is
> inserted:
> 
> Jan 12 10:37:19 dmz55 kernel: <2<>N2M>NINM IM INISMI AI S AIIS SAA
> 22cc2,,c ,  E2EIcIES,SIAS  AA
> E  I00
> Jan 12 10:37:19 dmz55 kernel:
> Jan 12 10:37:19 dmz55 kernel: S0
> Jan 12 10:37:19 dmz55 kernel:
> Jan 12 10:37:19 dmz55 kernel: <<22>>A
> Jan 12 10:37:19 dmz55 kernel:
> Jan 12 10:37:19 dmz55 kernel: 0
> Jan 12 10:37:28 dmz55 kernel: bce2: /usr/src/sys/dev/bce/if_bce.c(1533):
> Error: PHY read timeout!
>  phy = 1, reg = 0x0001
> 
> 
> What's are the best next steps to take in figuring this out?  Thanks in
> advance for any assistance.  Kernel boot log appending below.
> 

Are you using ASF/IMPI/UMP on bce2 or bce3?
If so would you try attached patch? Publicly available datasheet
lacks details on management firmware handling so I'm not sure what
is really happening here.
davidch may shed light on this(CCed).

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Index: sys/dev/bce/if_bce.c
===================================================================
--- sys/dev/bce/if_bce.c	(revision 202534)
+++ sys/dev/bce/if_bce.c	(working copy)
@@ -6423,7 +6423,11 @@
 	ifp = sc->bce_ifp;
 
 	/* Enable all critical blocks in the MAC. */
-	REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
+	if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
+	    (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716))
+		REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT_XI);
+	else
+		REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
 	REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
 	DELAY(20);
 

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