Date: Thu, 27 Apr 2000 10:01:44 -0700 (PDT) From: Matthew Dillon <dillon@apollo.backplane.com> To: Luoqi Chen <luoqi@watermarkgroup.com> Cc: bright@wintelcom.net, djb@ifa.au.dk, freebsd-smp@FreeBSD.ORG, smp@csn.net Subject: Re: hlt instructions and temperature issues Message-ID: <200004271701.KAA05490@apollo.backplane.com> References: <200004271654.e3RGsOv03195@lor.watermarkgroup.com>
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:> of instructions can run on cpu B between any two instructions running
:> on cpu A. So think it through... if you have sti + BLAH + hlt and
:> the 'nop' stalls for a long, long time, is it possible for an interrupt
:> to occur?
:>
:I don't quite get the question... Are you talking about we can't have BLAH
:between sti and hlt? I think you are right. But we don't really need the
:BLAH, as Steve has said, the idle cpu already has the lowest TPR.
:-lq
What happens when both cpu's go idle? As far as I can tell, when both
cpu's go idle it is possible for an interrupt to occur on one or the
other just at the point after the STI instruction when you are
messing with the APIC, before the HLT instruction.
Intel guarentees that an STI+HLT combination will not interrupt in the
middle as long as the HLT instruction immediately follows the STI
instruction. If you have a single instruction inserted inbetween them,
that guarentee goes out the window.
-Matt
Matthew Dillon
<dillon@backplane.com>
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