Date: Tue, 23 Mar 2010 20:12:53 +0000 (UTC) From: Marcel Moolenaar <marcel@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r205535 - head/sys/powerpc/mpc85xx Message-ID: <201003232012.o2NKCrsh075564@svn.freebsd.org>
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Author: marcel Date: Tue Mar 23 20:12:53 2010 New Revision: 205535 URL: http://svn.freebsd.org/changeset/base/205535 Log: Add definitions for a 4th PCI host controller. No Freescale processor has all 4 implemented, but across the processors we now support all the combinations. For example, the MPC8533 doesn't have a PCI controller at 0xA0000, but does at 0xB0000. Modified: head/sys/powerpc/mpc85xx/ocpbus.c head/sys/powerpc/mpc85xx/ocpbus.h Modified: head/sys/powerpc/mpc85xx/ocpbus.c ============================================================================== --- head/sys/powerpc/mpc85xx/ocpbus.c Tue Mar 23 20:08:18 2010 (r205534) +++ head/sys/powerpc/mpc85xx/ocpbus.c Tue Mar 23 20:12:53 2010 (r205535) @@ -152,6 +152,10 @@ ocpbus_write_law(int trgt, int type, u_l addr = 0xA0000000; size = 0x10000000; break; + case OCP85XX_TGTIF_PCI3: + addr = 0xB0000000; + size = 0x10000000; + break; default: return (EINVAL); } @@ -170,6 +174,10 @@ ocpbus_write_law(int trgt, int type, u_l addr = 0xfee20000; size = 0x00010000; break; + case OCP85XX_TGTIF_PCI3: + addr = 0xfee30000; + size = 0x00010000; + break; default: return (EINVAL); } @@ -188,7 +196,7 @@ static int ocpbus_probe(device_t dev) { - device_set_desc(dev, "On-Chip Peripherals bus"); + device_set_desc(dev, "Freescale on-chip peripherals bus"); return (BUS_PROBE_DEFAULT); } @@ -210,6 +218,7 @@ ocpbus_attach(device_t dev) ocpbus_mk_child(dev, OCPBUS_DEVTYPE_PCIB, 0); ocpbus_mk_child(dev, OCPBUS_DEVTYPE_PCIB, 1); ocpbus_mk_child(dev, OCPBUS_DEVTYPE_PCIB, 2); + ocpbus_mk_child(dev, OCPBUS_DEVTYPE_PCIB, 3); ocpbus_mk_child(dev, OCPBUS_DEVTYPE_TSEC, 0); ocpbus_mk_child(dev, OCPBUS_DEVTYPE_TSEC, 1); ocpbus_mk_child(dev, OCPBUS_DEVTYPE_TSEC, 2); @@ -338,6 +347,10 @@ const struct ocp_resource mpc8555_resour OCP85XX_PCI_SIZE}, {OCPBUS_DEVTYPE_PCIB, 2, SYS_RES_MEMORY, 1, 0, OCP85XX_TGTIF_PCI2}, {OCPBUS_DEVTYPE_PCIB, 2, SYS_RES_IOPORT, 1, 0, OCP85XX_TGTIF_PCI2}, + {OCPBUS_DEVTYPE_PCIB, 3, SYS_RES_MEMORY, 0, OCP85XX_PCI3_OFF, + OCP85XX_PCI_SIZE}, + {OCPBUS_DEVTYPE_PCIB, 3, SYS_RES_MEMORY, 1, 0, OCP85XX_TGTIF_PCI3}, + {OCPBUS_DEVTYPE_PCIB, 3, SYS_RES_IOPORT, 1, 0, OCP85XX_TGTIF_PCI3}, {OCPBUS_DEVTYPE_LBC, 0, SYS_RES_MEMORY, 0, OCP85XX_LBC_OFF, OCP85XX_LBC_SIZE}, Modified: head/sys/powerpc/mpc85xx/ocpbus.h ============================================================================== --- head/sys/powerpc/mpc85xx/ocpbus.h Tue Mar 23 20:08:18 2010 (r205534) +++ head/sys/powerpc/mpc85xx/ocpbus.h Tue Mar 23 20:12:53 2010 (r205535) @@ -50,6 +50,7 @@ #define OCP85XX_TGTIF_PCI0 0 #define OCP85XX_TGTIF_PCI1 1 #define OCP85XX_TGTIF_PCI2 2 +#define OCP85XX_TGTIF_PCI3 3 #define OCP85XX_TGTIF_LBC 4 #define OCP85XX_TGTIF_RAM_INTL 11 #define OCP85XX_TGTIF_RIO 12 @@ -86,6 +87,7 @@ #define OCP85XX_PCI0_OFF 0x08000 #define OCP85XX_PCI1_OFF 0x09000 #define OCP85XX_PCI2_OFF 0x0A000 +#define OCP85XX_PCI3_OFF 0x0B000 #define OCP85XX_PCI_SIZE 0x1000 #define OCP85XX_TSEC0_OFF 0x24000 #define OCP85XX_TSEC1_OFF 0x25000
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