Date: Sat, 12 Mar 2005 08:05:03 +0000 From: David Malone <dwmalone@maths.tcd.ie> To: Daniel Eriksson <daniel_k_eriksson@telia.com> Cc: 'FreeBSD Current' <freebsd-current@freebsd.org> Subject: Re: Higher interrupt rate after recent SMP/APIC timer changes? Message-ID: <20050312080503.GA99089@salmon.maths.tcd.ie> In-Reply-To: <!~!UENERkVCMDkAAQACAAAAAAAAAAAAAAAAABgAAAAAAAAA0VcX9IoJqUaXPS8MjT1PdsKAAAAQAAAAeMYUhtckfk%2BR4a3yIBKgtAEAAAAA@telia.com>
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On Fri, Mar 11, 2005 at 11:51:40PM +0100, Daniel Eriksson wrote: > This is an SMP box (dual AMD AthlonMP) running with HZ=2000 and POLLING > enabled. Should I worry about the 4k intr/sec reported for lapic0 and > lapic1, or is this the way things should be? I believe this is what you should expect. The when using the lapic for timers, the lapic is programmed to interrupt at HZ*2 and then other timers are generated. See the commit messages for version 1.14 and 1.13 at: http://www.freebsd.org/cgi/cvsweb.cgi/src/sys/i386/i386/local_apic.c for more details. (There is also one lapic per processor - previously one timer interrupt would happen and then the processer that handeled that interrupt would have to forward it to other processors.) David.home | help
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