Date: Tue, 12 Nov 2013 17:26:08 +0400 From: Sergey Ryazanov <ryazanov.s.a@gmail.com> To: Nick Kossifidis <mickflemm@gmail.com> Cc: ath5k-devel@lists.ath5k.org, freebsd-wireless@freebsd.org Subject: Re: [ath5k-devel] Atheros AR5xxx DSSS-OFDM mode support Message-ID: <CAHNKnsTNEASMbHiqT7JWjczJnRCNsH22YdsgUo37sYJsS%2Ba-zA@mail.gmail.com> In-Reply-To: <52821DFC.60203@gmail.com> References: <CAHNKnsShTMiH-Bo%2BT0ydwFwpgoTd-Mx-BZXjP-1xoCE%2Bw-vzkQ@mail.gmail.com> <52821DFC.60203@gmail.com>
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2013/11/12 Nick Kossifidis <mickflemm@gmail.com>: > On Tue 12 Nov 2013 11:55:43 AM GMT, Sergey Ryazanov wrote: >> Hi list, >> >> we test pretty old hardware based on AR5414 chip with pretty old >> madwifi driver, which even use binary hal. Our spectral analyzer shows >> that in 2.4GHz band this chip transmits OFDM-preamble with any of the >> OFDM rates (6-54 mbps), instead of .11b-compatable DSSS-preamble. Does >> anybody could provide some clue: is this chip supports DSSS-OFDM mode >> according to section 19.7 of IEEE 802.11-2012? >> >> When I digging the ath5k code I faced the AR_PHY_MODE (0xa200) >> register, which seems to controls the behavior of chip. This register >> contains two interesting bit: >> AR_PHY_MODE_MOD_CCK bit 0 (0x00000001) >> AR_PHY_MODE_MOD_DYN bit 3 (0x00000004) >> >> If I am correctly understand, _MOD_DYN just enables the CCK (DSSS) >> block. But what the purpose of the AR_PHY_MODE_MOD_CCK bit? >> > > From what I know: > MOD_DYN = CCK + OFDM (for g) > MOD_CCK = CCK only (for b) > Thank you Nick, for your quick answer, may be you know, why we need such explicit option (I mean MOD_CCK bit)? If we would like to act as pure dot11b node, then we could simply limit rate set to DSSS/CCK rates only. Did you know something about DSSS-OFDM mode support in the AR5xxx chips, is it possible at all? -- BR, Sergey
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