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Date:      Wed, 1 Jun 2011 18:42:44 +0000 (UTC)
From:      Pyun YongHyeon <yongari@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r222581 - head/sys/dev/usb/net
Message-ID:  <201106011842.p51Igi4A082383@svn.freebsd.org>
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Author: yongari
Date: Wed Jun  1 18:42:44 2011
New Revision: 222581
URL: http://svn.freebsd.org/changeset/base/222581

Log:
  Poke correct GPIO pins for newer axe(4) controllers with Marvell
  PHY. Newer models seem to use different LED mode that requires
  enabling both GPIO1 and GPIO2.
  
  Tested by:	marcel

Modified:
  head/sys/dev/usb/net/if_axe.c

Modified: head/sys/dev/usb/net/if_axe.c
==============================================================================
--- head/sys/dev/usb/net/if_axe.c	Wed Jun  1 18:27:13 2011	(r222580)
+++ head/sys/dev/usb/net/if_axe.c	Wed Jun  1 18:42:44 2011	(r222581)
@@ -514,7 +514,7 @@ static void
 axe_ax88178_init(struct axe_softc *sc)
 {
 	struct usb_ether *ue;
-	int gpio0, phymode;
+	int gpio0, ledmode, phymode;
 	uint16_t eeprom, val;
 
 	ue = &sc->sc_ue;
@@ -528,9 +528,11 @@ axe_ax88178_init(struct axe_softc *sc)
 	if (eeprom == 0xffff) {
 		phymode = AXE_PHY_MODE_MARVELL;
 		gpio0 = 1;
+		ledmode = 0;
 	} else {
 		phymode = eeprom & 0x7f;
 		gpio0 = (eeprom & 0x80) ? 0 : 1;
+		ledmode = eeprom >> 8;
 	}
 
 	if (bootverbose)
@@ -548,9 +550,22 @@ axe_ax88178_init(struct axe_softc *sc)
 			AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4);
 			AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
 			    hz / 32);
-		} else
+		} else {
 			AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
-			    AXE_GPIO1_EN, hz / 32);
+			    AXE_GPIO1_EN, hz / 3);
+			if (ledmode == 1) {
+				AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3);
+				AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN,
+				    hz / 3);
+			} else {
+				AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
+				    AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
+				AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
+				    AXE_GPIO2_EN, hz / 4);
+				AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
+				    AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
+			}
+		}
 		break;
 	case AXE_PHY_MODE_CICADA:
 	case AXE_PHY_MODE_CICADA_V2:

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