Date: Fri, 3 Mar 2006 00:01:29 +0200 From: Ruslan Ermilov <ru@FreeBSD.org> To: "M. Warner Losh" <imp@bsdimp.com> Cc: cvs-src@FreeBSD.org, gurney_j@resnet.uoregon.edu, src-committers@FreeBSD.org, scottl@samsco.org, cvs-all@FreeBSD.org Subject: Re: cvs commit: src/share/man/man9 bus_dma.9 Message-ID: <20060302220129.GA67620@ip.net.ua> In-Reply-To: <20060302.141520.53336566.imp@bsdimp.com> References: <20060302071849.GH29183@ip.net.ua> <20060302181629.GS840@funkthat.com> <20060302185507.GM29183@ip.net.ua> <20060302.141520.53336566.imp@bsdimp.com>
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On Thu, Mar 02, 2006 at 02:15:20PM -0700, M. Warner Losh wrote:
> Here's what I came up with earlier in the week.
>=20
Looks mostly good but it doesn't fix the types of DMA ops
as in my patch.
> Index: bus_dma.9
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> RCS file: /home/ncvs/src/share/man/man9/bus_dma.9,v
> retrieving revision 1.31
> diff -u -r1.31 bus_dma.9
> --- bus_dma.9 13 Dec 2005 17:07:52 -0000 1.31
> +++ bus_dma.9 2 Mar 2006 21:14:40 -0000
> @@ -265,14 +265,41 @@
> .It Dv BUS_DMASYNC_PREREAD
> Perform any synchronization required prior to an update of host memory b=
y the
> DMA read operation.
^^^^ write
> +.Pp
> +In other words, the driver is about to command the device to start
> +a DMA operation that transfers data from the
^ write
> +device to the memory described by this map.
> +And pending writes to this part of memory that the CPU might have queued
^^^ Any
> +up will either be discarded or be completed after this operation complet=
es.
> .It Dv BUS_DMASYNC_PREWRITE
> Perform any synchronization required after an update of host memory by t=
he CPU
> and prior to DMA write operations.
^^^^^ read
> +.Pp
> +In other words, the CPU flushes any cached writes to the area of memory
> +described by this map so they are visible when the device does its
> +DMA READ operation on the memory described by the map.
^^^^ right
> +An implementation may also use this to implement bounce buffers and
> +memory barriers.
> .It Dv BUS_DMASYNC_POSTREAD
> Perform any synchronization required after DMA read operations and prior=
to
^^^^ write
> CPU access to host memory.
> +.Pp
> +In other words, the CPU discards the cached values for the memory range
> +described by the map.
> +Future reads to the memory range described by the map will fetch the val=
ues
^^ from
> +from memory.
> +An implementation is free to reload the cache before any driver initiated
driver-initiated
> +reads to this memory.
^^ from
> +An implementation may also use this to implement bounce buffers and
> +memory barriers.
> .It Dv BUS_DMASYNC_POSTWRITE
> Perform any synchronization required after DMA write operations.
^^^^^ read
> +.Pp
> +In other words, this is completely useless.
> +The driver writer has noticed that the device has indicated the DMA READ
> +operation has completed.
> +It is theoretically possible that this would cause the device to do some=
thing
> +but it is unclear what.
> .El
> .It Vt bus_dma_lock_t
> Client specified lock/mutex manipulation method.
Cheers,
--=20
Ruslan Ermilov
ru@FreeBSD.org
FreeBSD committer
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