Date: Wed, 24 Apr 2024 18:31:41 GMT From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org Subject: git: ef80df0a7191 - main - arm64/vmm: Ensure the tlbi has completed Message-ID: <202404241831.43OIVfGT091185@gitrepo.freebsd.org>
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The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=ef80df0a71912500ad84060334a24e903869f00b commit ef80df0a71912500ad84060334a24e903869f00b Author: Andrew Turner <andrew@FreeBSD.org> AuthorDate: 2024-04-15 14:36:20 +0000 Commit: Andrew Turner <andrew@FreeBSD.org> CommitDate: 2024-04-24 18:17:19 +0000 arm64/vmm: Ensure the tlbi has completed Ensure the TLB is invalidated before enabling the EL2 MMU. Without this the TLB may be in an inconsistant state leading to a possible exception when enabling the MMU. PR: 277559 Reviewed by: markj Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D44799 --- sys/arm64/vmm/vmm_hyp_exception.S | 3 +++ 1 file changed, 3 insertions(+) diff --git a/sys/arm64/vmm/vmm_hyp_exception.S b/sys/arm64/vmm/vmm_hyp_exception.S index 77cb8cfd6cd7..0e8b31ae8b12 100644 --- a/sys/arm64/vmm/vmm_hyp_exception.S +++ b/sys/arm64/vmm/vmm_hyp_exception.S @@ -215,7 +215,10 @@ LENTRY(handle_hyp_init) /* Load the base address for the translation tables */ msr ttbr0_el2, x0 /* Invalidate the TLB */ + dsb ish tlbi alle2 + dsb ishst + isb /* Use the same memory attributes as EL1 */ mrs x9, mair_el1 msr mair_el2, x9
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