Date: Wed, 11 Jun 1997 16:29:39 +0000 () From: "Rodney W. Grimes" <rgrimes@GndRsh.aac.dev.com> To: roberto@keltia.freenix.fr (Ollivier Robert) Cc: hardware@FreeBSD.ORG Subject: Re: poor memory bandwidth on ABIT IT5H rev 1.5 Message-ID: <199706111629.JAA00216@GndRsh.aac.dev.com> In-Reply-To: <19970611093951.33576@keltia.freenix.fr> from Ollivier Robert at "Jun 11, 97 09:39:51 am"
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... > > The major limitation of the VX chip set is that it only supports > > 64MB of DRAM covered by secondary cache, so it is no good for > > server machines with a few hundred MB of RAM ... > > Yes, I don't understand why they keep this stupid limit (except for > marketing reasons that is). It is a technical limitation, you can cache 64MB of memory using a single 8 bit tag ram, if you want to cache more than that you need a wider tag ram, and more bits between the cache controller chip and the tags, and a wider tag comparitor. Those the cost to do this is small when you consider that 95% of the target market for the chipset is not going to use these added features it becomes a simple economic decision. Is what I don't like is that Intel tends to make it hard to find out the detailed limitations of each chipset the produce. They have gotten better over time, but they don't come out right up front and say things about some of the more important details (like the fact that the TX chip set has no Parity logic :-(). -- Rod Grimes rgrimes@gndrsh.aac.dev.com Accurate Automation, Inc. Reliable computers for FreeBSD
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