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Date:      Tue, 25 Oct 2016 00:47:16 +0200
From:      Emmanuel Vadot <manu@bidouilliste.com>
To:        Mark Millard <markmi@dsl-only.net>
Cc:        freebsd-arm <freebsd-arm@freebsd.org>, FreeBSD-STABLE Mailing List <freebsd-stable@freebsd.org>
Subject:   Re: BPi-M3 under stable/11 details: boots but with only 4 cores used for SMP --of 8 cores present. . .
Message-ID:  <20161025004716.b162f20383228707c610dbf1@bidouilliste.com>
In-Reply-To: <71D914B0-6D3E-424D-B173-7EDBF883B3FE@dsl-only.net>
References:  <E3FF801C-6BC5-4A4B-9749-64F06A3FFB98@dsl-only.net> <20161024230048.a440664797abd796eac08243@bidouilliste.com> <71D914B0-6D3E-424D-B173-7EDBF883B3FE@dsl-only.net>

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 Ah yes, well same thing, we don't support cluster :)

On Mon, 24 Oct 2016 15:42:40 -0700
Mark Millard <markmi@dsl-only.net> wrote:

> On 2016-Oct-24, at 2:00 PM, Emmanuel Vadot <manu at bidouilliste.com> wro=
te:
>=20
>=20
> > Hello Mark,
> >=20
> > The A83T is BIG/Little IIRC and we don't support that. That's why you
> > only see 4 cores on the 8.
>=20
> That is not what I get from reading the A83T documentation. All the CPU r=
eferences are to the same type of CPU for each of the 8. But there is a NUM=
A-ish pair of "clusters" of "CPU"s without a common L2-cache or other cache=
 across the clusters.
>=20
> http://linux-sunxi.org/A83T says . . .
>=20
> > This SoC does NOT comply with the ARM big.LITTLE architecture, therefor=
e it is in no way energy efficent and gets very hot.
>=20
>=20
> > CPU:
> > 	? ARM Cortex-A7 Octa-Core
>=20
>=20
> A83T_Datasheet_v1.3_20150510.pdf says:
>=20
> > Main features of A83T include:
> > ? CPU architecture: Based on an octa-core CortexTM-A7 CPU architecture,=
 . . ..
>=20
>=20
> > 2.1. CPU Architecture
> >=20
> > 	? ARMv7 ISA standard instruction set plus Thumb-2 and Jazeller RCT
> >=20
> > 	? NEON with SIMD and VFPv4
> >=20
> > 	? Support LPAE
> >=20
> > 	? 32KB I-cache and 32KB D-cache per CPU
> >=20
> > 	? 1MB L2-cache
>=20
> The "A883T Block Diagram (Figure 3-1 page labeled 12) simply says "A7 x 8=
".
>=20
> A83T_User_Manual_v1.5.1_20150513.pdf has some more detailed diagrams and =
more information. . .
>=20
> There are two CPU Clusters (0 and  1). It is more of a NUMA context due t=
o caching within each cluster that is not across the clusters. This documen=
t's wording is more explicit, mentioning clusters for the L2-cache level (p=
age labeled 51) in even its basic description of caches in the A83T archtie=
cture:
>=20
> > 2.1.1. CPU Architecture
> >=20
> > The A83T platform is based on octa-core CortexTM-A7 CPU architecture.
> >=20
> > 	? ?  ARMv7 ISA standard instruction set plus Thumb-2 and Jazeller RCT
> >=20
> > 	? ?  NEON with SIMD and VFPv4 support
> >=20
> > 	? ?  Support LPAE
> >=20
> > 	? ?  32KB I-cache and 32KB D-cache per CPU
> >=20
> > 	? ?  1MB L2-cache(512KB per Cluster)
>=20
>=20
> See this document's Figure 3-1 "System Bus Tree" (on the page labeled 66).
>=20
> From what I read one can control clock frequencies per cluster but it is =
allowed to have them both the same all the time that frequencies are stable=
 for a while.
>=20
> And I'll stop with the details that I see with that.
>=20
> There may be some folks around with knowledge of more detail that might w=
ell be able to say "but it is not NUMA like for these details . . .". By no=
 mean have I analyzed all the consequences of all the details.
>=20
> But I find no evidence of BIG/Little use of different classes of cores at=
 necessarily different cock rates and the like. As much as I've looked at l=
ooks more symmetric than that.
>=20
>=20
>=20
> > cpulist0 shows 8 core because every core in is the dtb.
> >=20
> > On Mon, 24 Oct 2016 09:04:35 -0700
> > Mark Millard <markmi@dsl-only.net> wrote:
> >=20
> >> The is for a Banana Pi M3 V1.2 board with the barrel power connector. =
The 5V 2A supply that I had to fit the barrel hole can not power the board =
sufficiently to boot --even when no fan is being powered. In order to boot =
with a fan I have both that and an official rpi3 power supply plugged in. T=
he rpi3 power supply will not power the GPIO fan connections but can boot t=
he board by itself (V5.1v and 2.5A but cell phone charger cabling/connectio=
ns). I've got a heat sink on the CPU as well.
> >>=20
> >>> root@bananapi-m3:~ # uname -apKU
> >>> FreeBSD bananapi-m3 11.0-STABLE FreeBSD 11.0-STABLE #0 r307797M: Mon =
Oct 24 00:41:16 PDT 2016     markmi@FreeBSDx64:/usr/local/src/crochet/work/=
obj/arm.armv6/usr/src/sys/ALLWINNER  arm armv6 1100505 1
> >>> 100505
> >>=20
> >>> root@bananapi-m3:~ # freebsd-version -ku
> >>> 11.0-STABLE
> >>> 11.0-STABLE
> >>=20
> >> In the below note that "FreeBSD/SMP: Multiprocessor System Detected: 4=
 CPUs" but cpulist0 shows cpu0 through cpu7. For now: So much for seeing ho=
w buildworld/buildkernel would go using all 8 cores.
> >>=20
> >> (Note: the serial connection tends to drop some text sometimes. That m=
ay have happened some for the below.)
> >>=20
> >>> root@bananapi-m3:~ # dmesg | more
> >>> Copyright (c) 1992-2016 The FreeBSD Project.
> >>> Copyright (c) 1979, 1980, 1983, 1986, 1988, 1989, 1991, 1992, 1993, 1=
994
> >>>       The Regents of the University of California. All rights reserve=
d.
> >>> FreeBSD is a registered trademark of The FreeBSD Foundation.
> >>> FreeBSD 11.0-STABLE #0 r307797M: Mon Oct 24 00:41:16 PDT 2016
> >>>   markmi@FreeBSDx64:/usr/local/src/crochet/work/obj/arm.armv6/usr/src=
/sys/ALLWINNER arm
> >>> FreeBSD clang version 3.8.0 (tags/RELEASE_380/final 262564) (based on=
 LLVM 3.8.0)
> >>> VT: init without driver.
> >>> CPU: Cortex A7 rev 5 (Cortex-A core)
> >>> Supported features: ARM_ISA THUMB2 JAZELLE THUMBEE ARMv4 Security_Ext
> >>> WB enabled LABT branch prediction disabled
> >>> LoUU:2 LoC:3 LoUIS:2=20
> >>> Cache level 1:=20
> >>> 32KB/64B 4-way data cache WB Read-Alloc Write-Alloc
> >>> 32KB/32B 2-way instruction cache Read-Alloc
> >>> Cache level 2:=20
> >>> 512KB/64B 8-way unified cache WB Read-Alloc Write-Alloc
> >>> real memory  =3D 2147483648 (2048 MB)
> >>> avail memory =3D 2090852352 (1993 MB)
> >>> FreeBSD/SMP: Multiprocessor System Detected: 4 CPUs
> >>> random: entropy device external interface
> >>> kbd0 at kbdmux0
> >>> ofwbus0: <Open Firmware Device Tree>
> >>> aw_ccu0: <Allwinner Clock Control Unit> on ofwbus0
> >>> clk_fixed0: <Fixed clock> on aw_ccu0
> >>> clk_fixed1: <F PLL Clock> mem 0x1c20028-0x1c2002b on aw_ccu0
> >>> clk_fixed3: <Fixed factor clock> on aw_ccu0
> >>> aw_ahbclk0: <Allwinner AHB Clock> mem 0x1c20054-0x1c20057 on aw_ccu0
> >>> aw_apbclk0: <Allwinner APB Clock> mem 0x1c20054-0x1c20057 on aw_ccu0
> >>> aw_apbclk1: <Allwinner APB Clock> mem 0x1c20058-0x1c2005b on aw_ccu0
> >>> aw_ahbclk1: <Allwinner AHB Clock> mem 0x1c2005c-0x1c2005f on aw_ccu0
> >>> aw_gate0: <Allwinner Bus Clock Gates> mem 0x1c20060-0x1c2006f on aw_c=
cu0
> >>> aw_mmcclk0: <Allwinner MMC Clock> mem 0x1c20088-0x1c2clk1: <Allwinner=
 MMC Clock> mem 0x1c2008c-0x1c2008f on aw_ccu0
> >>> aw_mmcclk2: <Allwinner MMC Clock> mem 0x1c20090-0x1c20093 on aw_ccu0
> >>> aw_cpusclk0: <Allwinner CPUS Clock> mem 0x1f01400-0x1f01403 on aw_ccu0
> >>> clk_fixed4: <Fixed factor clock> on aw_ccu0
> >>> aw_apbclk2: <Allwinner APB Clock> mem 0x1f0140c-0x1f0140f on aw_ccu0
> >>> aw_gate1: <Allwinner APB0 Clock Gates> mem 0x1f01428-0x1f0142b on aw_=
ccu0
> >>> aw_pll1: <Allwinner PLL Clock> mem 0x1c20044-0x1c20047 on aw_ccu0
> >>> aw_usbclk0: <Allwinner USB Clocks> mem 0x1c200cc-0x1c200cf on aw_ccu0
> >>> clk_fixed5: <Fixed clr GMAC Clock> mem 0x1c00030-0x1c00033 on aw_ccu0
> >>> simplebus0: <Flattened device tree simple bus> on ofwbus0
> >>> aw_reset0: <Allwinner Module Resets> mem 0x1c202c0-0x1c202cb on simpl=
ebus0
> >>> aw_reset1: <Allwinner Module Resets> mem 0x1c202d0-0x1c202d3 on simpl=
ebus0
> >>> aw_reset2: <Allwinner Module Resets> mem 0x1c202d8-0x1c202db on simpl=
ebus0
> >>> aw_reset3: <Allwinner Module Resets> mem 0x1f014b0-0x1f014b3 on simpl=
ebus0
> >>> iichb0: <Allwinner Integrated I2C Bus Controller> mem 0x1c2ac00-0x1c2=
afff on simplebus0
> >>> iicbus0: hb0
> >>> iichb1: <Allwinner Integrated I2C Bus Controller> mem 0x1c2b000-0x1c2=
b3ff on simplebus0
> >>> iicbus1: <OFW I2C bus> on iichb1
> >>> iichb2: <Allwinner Integrated I2C Bus Controller> mem 0x1c2b400-0x1c2=
b7ff on simplebus0
> >>> iicbus2: <OFW I2C bus> on iichb2
> >>> regfix0: <Fixed Regulator> on ofwbus0
> >>> regfix1: <Fixed Regulator> on ofwbus0
> >>> regfix2: <Fixed Regulator> on ofwbus0
> >>> regfix3: <Fixed Regulator> on ofwbus0
> >>> regfix4: <Fixed Regulator> on ofwbus0
> >>> aw_sid0: <Allwinner Secure ID Controller> mem 0x1c14000-0x1c143ff on =
simplebus0
> >>> awusbphy0: <Allwinner USB PHY> on simplebu,0x1c86000-0x1c87fff on sim=
plebus0
> >>> gic0: pn 0x20, arch 0x2, rev 0x1, implementer 0x43b irqs 224
> >>> gpio0: <Allwinner GPIO/Pinmux controller> mem 0x1c20800-0x1c20bff on =
simplebus0
> >>> gpiobus0: <OFW GPIO bus> on gpio0
> >>> gpio1: <Allwinner GPIO/Pinmux controller> mem 0x1f02c00-0x1f02fff on =
simplebus0
> >>> gpiobus1: <OFW GPIO bus> on gpio1
> >>> aw_nmi0: <Allwinner NMI Controller> mem 0x1f00c0c-0x1f00c43 on simple=
bus0
> >>> generic_timer0: <ARMv7 Generic Timer> on ofwbus0
> >>> Timecounter "cy 24000000 Hz quality 1000
> >>> Event timer "ARM MPCore Eventtimer" frequency 24000000 Hz quality 1000
> >>> cpulist0: <Open Firmware CPU Group> on ofwbus0
> >>> cpu0: <Open Firmware CPU> on cpulist0
> >>> cpu1: <Open Firmware CPU> on cpulist0
> >>> cpu2: <Open Firmware CPU> on cpulist0
> >>> cpu3: <Open Firmware CPU> on cpulist0
> >>> cpu4: <Open Firmware CPU> on cpulist0
> >>> cpu5: <Open Firmware CPU> on cpulist0
> >>> cpu6: <Open Firmware CPU> on cpulist0
> >>> cpu7: <Open Firmware CPU> on cpulist0
> >>> a10_mmc0: <Allwinner Integrated MMC/SD controller> mem 0x1c0f000-0x1c=
0ffff on simplebus0
> >>> mmc0: <MMC/SD bus> on a10_mmc0
> >>> a10_mmc1: <Allwinner Integrated MMC/SD controller> mem 0x1c11000-0x1c=
11fff on simplebus0
> >>> mmc1: <MMC/SD bus> on a10_mmc1
> >>> gpioc0: <GPIO controller> on gpio0
> >>> aw_wdog0: <Allwinner A31 Watchdog> mem 0x1c20ca0-0x1c20cbf on simpleb=
us0
> >>> uart0: <Non-standard ns8250 class UART with FIFOs> mem 0x1c28000-0x1c=
283ff on simplebus0
> >>> uart0: console (480769,n,8,1)
> >>> gpioc1: <GPIO controller> on gpio1
> >>> iichb3: <Allwinner RSB> mem 0x1f03400-0x1f037ff on simplebus0
> >>> iicbus3: <OFW I2C bus> on iichb3
> >>> iic0: <I2C generic I/O> on iicbus3
> >>> axp81x_pmu0: <X-Powers AXP81x Power Management Unit> at addr 0x746 on=
 iicbus3
> >>> gpiobus2: <OFW GPIO bus> on axp81x_pmu0
> >>> gpioled0: <GPIO led> at pin 0 on gpiobus2
> >>> gpioled1: <GPIO led> at pin 1 on gpiobus2
> >>> gpioc2: <GPIO controller> on axp81x_pmu0
> >>> iic1: <I2C generic I/O> on iicbus0
> >>> iic2: <I2C generic I/O> on iicbus1
> >>> iic3: <I2C generic I/O> on iicbus2
> >>> ehci0: <Allwinner Integrated USB 2.0 controller> mem 0x1c1a000-0x1c1a=
0ff on simplebus0
> >>> usbus0: EHCI version 1.0
> >>> usbus0 on ehci0
> >>> ehci1: <Allwinner Integrated USB 2.0 controller> mem 0x1c1b000-0x1c1b=
0ff on simplebus0
> >>> usbus1: EHCI version 1.0
> >>> usbus1 on ehci1
> >>> awg0: <Allwinner Gigabit Ethernet> mem 0x1c30000-0x1c300ff on simpleb=
us0
> >>> miibus0: <MII bus> on awg0
> >>> rgephy0: <RTL8169S/8110S/8211 1000BASE-T media interface> PHY 0 on mi=
ibus0
> >>> rgephy0:  none, 10baseT, 10baseT-FDX, 10baseT-FDX-flow, 100baseTX, 10=
0baseTX-FDX, 100baseTX-FDX-flow, 1000baseT, 1000baseT-master, 1000baseT-FDX=
, 1000baseT-FDX-master, 1000baseT-FDX-flow, 1000baseT-FD
> >>> X-flow-master, auto, auto-flow
> >>> rgephy1: <RTL8169S/8110S/8211 1000BASE-T media interface> PHY 1 on mi=
ibus0
> >>> rgephy1:  none, 10baseT, 10baseT-FDX, 10baseT-FDX-flow, 100baseTX, 10=
0baseTX-FDX, 100baseTX-FDX-flow, 1000baseT, 1000baseT-master, 1000baseT-FDX=
, 1000baseT-FDX-master, 1000baseT-FDX-flow, 1000baseT-FD
> >>> X-flow-master, auto, auto-flow
> >>> awg0: Ethernet address: f2:00:52:68:6d:d8
> >>> aw_thermal0: <Allwinner Thermal Sensor Controller> mem 0x1f04000-0x1f=
043ff on simplebus0
> >>> cryptosoft0: <software crypto>
> >>> Timecounters tick every 10.000 msec
> >>> usbus0: 480Mbps High Speed USB v2.0
> >>> usbus1: 480Mbps High Speed USB v2.0
> >>> ugen1.1: <Allwinner> at usbus1
> >>> ugen0.1: <Allwinner> at usbus0
> >>> uhub0: <Allwinner EHCI root HUB, class 9/0, rev 2.00/1.00, addr 1> on=
 usbus0
> >>> uhub1: <Allwinner EHCI root HUB, class 9/0, rev 2.00/1.00, addr 1> on=
 usbus1
> >>> mmcsd0: 32GB <SDHC 00000 1.0 SN A1535564 MFG 09/2015 by 27 SM> at mmc=
0 50.0MHz/4bit/65535-block
> >>> a10_mmc1: error rint: 0x00000100
> >>> a10_mmc1: error rint: 0x00000100
> >>> a10_mmc1: error rint: 0x00000100
> >>> a10_mmc1: error rint: 0x00000100
> >>> a10_mmc1: error rint: 0x00000100
> >>> a10_mmc1: error rint: 0x00000100
> >>> a10_mmc1: error rint: 0x00000100
> >>> a10_mmc1: error rint: 0x00000100
> >>> a10_mmc1: error rint: 0x00008018
> >>> a10_mmc1: error rint: 0x00000100
> >>> a10_mmc1: error rint: 0x00000100
> >>> a10_mmc1: error rint: 0x00000100
> >>> a10_mmc1: error rint: 0x00000100
> >>> mmcsd1: 8GB <MMCHC 8WPD3R 0.0 SN E7C6641B MFG 01/2000 by 21 0x0000> a=
t mmc1 50.0MHz/8bit/65535-block
> >>> Release APs
> >>> Trying to mount root from ufs:/dev/mmcsd0s2a [rw,noatime]...
> >>> warning: no time-of-day clock registered, system time will not be set=
 accurately
> >>> uhub0: 1 port with 1 removable, self powered
> >>> uhub1: 1 port with 1 removable, self powered
> >>> ugen0.2: <vendor 0x1a40> at usbus0
> >>> uhub2 on uhub0
> >>> uhub2: <vendor 0x1a40 USB 2.0 Hub, class 9/0, rev 2.00/1.11, addr 2> =
on usbus0
> >>> uhub2: 4 ports with 4 removable, self powered
> >>> ugen0.3: <vendor 0x05e3> at usbus0
> >>> umass0 on uhub2
> >>> umass0: <vendor 0x05e3 USB Storage, class 0/0, rev 2.00/0.16, addr 3>=
 on usbus0
> >>> (probe0:umass-sim0:0:0:0): INQUIRY. CDB: 12 00 00 00 24 00=20
> >>> (probe0:umass-sim0:0:0:0): CAM status: CCB request completed with an =
error
> >>> (probe0:umass-sim0:0:0:0): Retrying command
> >>> random: unblocking device.
> >>> awg0: link state changed to DOWN
> >>> (probe0:umass-sim0:0:0:0): INQUIRY. CDB: 12 00 00 00 24 00=20
> >>> (probe0:umass-sim0:0:0:0): CAM status: CCB request completed with an =
error
> >>> (probe0:umass-sim0:0:0:0): Retrying command
> >>> awg0: link state changed to UP
> >>> (probe0:umass-sim0:0:0:0): INQUIRY. CDB: 12 00 00 00 24 00=20
> >>> (probe0:umass-sim0:0:0:0): CAM status: CCB request completed with an =
error
> >>> (probe0:umass-sim0:0:0:0): Retrying command
> >>> (probe0:umass-sim0:0:0:0): INQUIRY. CDB: 12 00 00 00 24 00=20
> >>> (probe0:umass-sim0:0:0:0): CAM status: CCB request completed with an =
error
> >>> (probe0:umass-sim0:0:0:0): Retrying command
> >>> (probe0:umass-sim0:0:0:0): INQUIRY. CDB: 12 00 00 00 24 00=20
> >>> (probe0:umass-sim0:0:0:0): CAM status: CCB request completed with an =
error
> >>> (probe0:umass-sim0:0:0:0): Error 5, Retries exhausted
> >>=20
> >> So far the probe0 messages stop after just a few like the above.
> >>=20
> >> Also it looks like the 8GB eMMC (mmc1 / mmcsd1) is likely not supporte=
d yet.
> >>=20
> >> I have not yet tried connecting an external usb drive.
> >>=20
> >> Some structure of what was done with the cores shows in the sysctl -a =
output: cpu names 0-3 and 100-103.
> >>=20
> >> (Note: the serial connection tends to drop some text sometimes. That m=
ay have happened some for the below.)
> >>=20
> >>> root@bananapi-m3:~ # sysctl -a | grep cpu
> >>> kern.smp.cpus: 4
> >>> kern.smp.maxcpus: 4
> >>> kern.ccpu: 0
> >>> <cpu count=3D"4" mask=3D"f">0, 1, 2, 3</cpu>
> >>>   <cpu count=3D"4" mask=3D"f">0, 1, 2, 3</cpu>
> >>> kern.sched.cpusetsize: 4
> >>> kern.pin_pcpu_swi: 0
> >>> kern.vt.splash_cpu_duration: 10
> >>> kern.vt.splash_cpu_style: 2
> >>> kern.vt.splash_ncpu: 0
> >>> kern.vt.splash_cpu: 0
> >>> net.inet.tcp.per_cpu_timers: 0
> >>> debug.PMAP1changedcpu: 106
> >>> debug.cpufreq.verbose: 0
> >>> debug.cpufreq.lowest: 0
> >>> hw.ncpu: 4
> >>> dev.cpu.7.%parent: cpulist0
> >>> dev.cpu.7.%pnpinfo: name=3Dcpu@103 compat=3Darm,cortex-a7
> >>> dev.cpu.7.%location:=20
> >>> dev.cpu.7.%driver: cpu
> >>> dev.cpu.7.%desc: Open Firmware CPU
> >>> dev.cpu.6.%parent: cpulist0
> >>> dev.cpu.6.%pnpinfo: name=3Dcpu@102 compat=3Darm,cortex-a7
> >>> dev.cpu.6.%location:=20
> >>> dev.cpu.6.%driver: cpu
> >>> dev.cpu.6.%desc: Open Firmware CPU
> >>> dev.cpu.5.%parent: cpulist0
> >>> dev.cpu.5.%pnpinfo: name=3Dcpu@101 compat=3Darm,cortex-a7
> >>> dev.cpu.5.%location:=20
> >>> dev.cpu.5.%dri.5.%desc: Open Firmware CPU
> >>> dev.cpu.4.%parent: cpulist0
> >>> dev.cpu.4.%pnpinfo: name=3Dcpu@100 compat=3Darm,cortex-a7
> >>> dev.cpu.4.%location:=20
> >>> dev.cpu.4.%driver: cpu
> >>> dev.cpu.4.%desc: Open Firmware CPU
> >>> dev.cpu.3.%parent: cpulist0
> >>> dev.cpu.3.%pnpinfo: name=3Dcpu@3 compat=3Darm,cortex-a7
> >>> dev.cpu.3.%location:=20
> >>> dev.cpu.3.%driver: cpu
> >>> dev.cpu.3.%desc: Open Firmware CPU
> >>> dev.cpu.2.%parent: cpulist0
> >>> dev.cpu.2.%pnpinfo: name=3Dcpu@2 compat=3Darm,cortex-a7
> >>> dev.cpu.2.%location:=20
> >>> dev.cpu.2.%driver: cpu
> >>> dev.cpu.2.%desc: Open Firmware CPU
> >>> dev.cpu.1.%parent: cpulist0
> >>> dev.cpu.1.%location:=20
> >>> dev.cpu.1.%driver: cpu
> >>> dev.cpu.1.%desc: Open Firmware CPU
> >>> dev.cpu.0.%parent: cpulist0
> >>> dev.cpu.0.%pnpinfo: name=3Dcpu@0 compat=3Darm,cortex-a7
> >>> dev.cpu.0.%location:=20
> >>> dev.cpu.0.%driver: cpu
> >>> dev.cpu.0.%desc: Open Firmware CPU
> >>> dev.cpu.0.%parent: cpulist0
> >>> dev.cpulist.0.%parent: ofwbus0
> >>> dev.cpulist.0.%pnpinfo: name=3Dcpus
> >>> dev.cpulist.0.%location:=20
> >>> dev.cpulist.0.%driver: cpulist
> >>> dev.cpulist.0.%desc: Open Firmware CPU Group
> >>> dev.cpulist.%parent:=20
> >>> dev.aw_cpusclk.0.%parent: aw_ccu0
> >>> dev.aw_cpusclk.0.%pnpinfo: name=3Dclk@01f0140inner,sun8i-a83t-cpus-clk
> >>> dev.aw_cpusclk.0.%location:=20
> >>> dev.aw_cpusclk.0.%driver: aw_cpusclk
> >>> dev.aw_cpusclk.0.%desc: Allwinner CPUS Clock
> >>> dev.aw_cpusclk.%parent:=20
> >>> security.jail.param.cpuset.id: 0
> >>=20
> >>=20
> >>=20
> >> =3D=3D=3D
> >> Mark Millard
> >> markmi at dsl-only.net
> >>=20
>=20
> >=20
> > --=20
> > Emmanuel Vadot <manu@bidouilliste.com> <manu@freebsd.org>
>=20
> =3D=3D=3D
> Mark Millard
> markmi at dsl-only.net


--=20
Emmanuel Vadot <manu@bidouilliste.com> <manu@freebsd.org>



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