Date: Wed, 3 Feb 2016 13:47:50 +0000 (UTC) From: Michal Meloun <mmel@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r295207 - in head/sys/arm: arm include Message-ID: <201602031347.u13DloCJ059825@repo.freebsd.org>
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Author: mmel Date: Wed Feb 3 13:47:50 2016 New Revision: 295207 URL: https://svnweb.freebsd.org/changeset/base/295207 Log: ARM: Replace only once used cpu_icache_sync_all() by ranged equivalent. Remove it from cpu_functions table. Modified: head/sys/arm/arm/cpufunc.c head/sys/arm/arm/cpufunc_asm_arm11x6.S head/sys/arm/arm/cpufunc_asm_arm9.S head/sys/arm/arm/cpufunc_asm_armv5_ec.S head/sys/arm/arm/cpufunc_asm_armv7.S head/sys/arm/arm/cpufunc_asm_fa526.S head/sys/arm/arm/elf_machdep.c head/sys/arm/arm/genassym.c head/sys/arm/include/cpufunc.h Modified: head/sys/arm/arm/cpufunc.c ============================================================================== --- head/sys/arm/arm/cpufunc.c Wed Feb 3 12:11:07 2016 (r295206) +++ head/sys/arm/arm/cpufunc.c Wed Feb 3 13:47:50 2016 (r295207) @@ -110,7 +110,6 @@ struct cpu_functions arm9_cpufuncs = { /* Cache operations */ - arm9_icache_sync_all, /* icache_sync_all */ arm9_icache_sync_range, /* icache_sync_range */ arm9_dcache_wbinv_all, /* dcache_wbinv_all */ @@ -162,7 +161,6 @@ struct cpu_functions armv5_ec_cpufuncs = /* Cache operations */ - armv5_ec_icache_sync_all, /* icache_sync_all */ armv5_ec_icache_sync_range, /* icache_sync_range */ armv5_ec_dcache_wbinv_all, /* dcache_wbinv_all */ @@ -213,7 +211,6 @@ struct cpu_functions sheeva_cpufuncs = { /* Cache operations */ - armv5_ec_icache_sync_all, /* icache_sync_all */ armv5_ec_icache_sync_range, /* icache_sync_range */ armv5_ec_dcache_wbinv_all, /* dcache_wbinv_all */ @@ -264,7 +261,6 @@ struct cpu_functions pj4bv7_cpufuncs = { armv7_tlb_flushID_SE, /* tlb_flushD_SE */ /* Cache operations */ - armv7_idcache_wbinv_all, /* icache_sync_all */ armv7_icache_sync_range, /* icache_sync_range */ armv7_dcache_wbinv_all, /* dcache_wbinv_all */ @@ -316,7 +312,6 @@ struct cpu_functions xscale_cpufuncs = { /* Cache operations */ - xscale_cache_syncI, /* icache_sync_all */ xscale_cache_syncI_rng, /* icache_sync_range */ xscale_cache_purgeD, /* dcache_wbinv_all */ @@ -368,7 +363,6 @@ struct cpu_functions xscalec3_cpufuncs = /* Cache operations */ - xscalec3_cache_syncI, /* icache_sync_all */ xscalec3_cache_syncI_rng, /* icache_sync_range */ xscalec3_cache_purgeD, /* dcache_wbinv_all */ @@ -420,7 +414,6 @@ struct cpu_functions fa526_cpufuncs = { /* Cache operations */ - fa526_icache_sync_all, /* icache_sync_all */ fa526_icache_sync_range, /* icache_sync_range */ fa526_dcache_wbinv_all, /* dcache_wbinv_all */ @@ -472,7 +465,6 @@ struct cpu_functions arm1176_cpufuncs = /* Cache operations */ - arm11x6_icache_sync_all, /* icache_sync_all */ arm11x6_icache_sync_range, /* icache_sync_range */ arm11x6_dcache_wbinv_all, /* dcache_wbinv_all */ @@ -528,7 +520,6 @@ struct cpu_functions cortexa_cpufuncs = /* Cache operations */ - armv7_icache_sync_all, /* icache_sync_all */ armv7_icache_sync_range, /* icache_sync_range */ armv7_dcache_wbinv_all, /* dcache_wbinv_all */ Modified: head/sys/arm/arm/cpufunc_asm_arm11x6.S ============================================================================== --- head/sys/arm/arm/cpufunc_asm_arm11x6.S Wed Feb 3 12:11:07 2016 (r295206) +++ head/sys/arm/arm/cpufunc_asm_arm11x6.S Wed Feb 3 13:47:50 2016 (r295207) @@ -132,12 +132,6 @@ ENTRY_NP(arm11x6_dcache_wbinv_all) RET END(arm11x6_dcache_wbinv_all) -ENTRY_NP(arm11x6_icache_sync_all) - Flush_D_cache(r0) - Invalidate_I_cache(r0, r1) - RET -END(arm11x6_icache_sync_all) - ENTRY_NP(arm11x6_icache_sync_range) add r1, r1, r0 sub r1, r1, #1 Modified: head/sys/arm/arm/cpufunc_asm_arm9.S ============================================================================== --- head/sys/arm/arm/cpufunc_asm_arm9.S Wed Feb 3 12:11:07 2016 (r295206) +++ head/sys/arm/arm/cpufunc_asm_arm9.S Wed Feb 3 13:47:50 2016 (r295207) @@ -85,9 +85,7 @@ ENTRY_NP(arm9_icache_sync_range) subs r1, r1, ip bhi .Larm9_sync_next mov pc, lr -END(arm9_icache_sync_range) -ENTRY_NP(arm9_icache_sync_all) .Larm9_icache_sync_all: /* * We assume that the code here can never be out of sync with the @@ -109,7 +107,7 @@ ENTRY_NP(arm9_icache_sync_all) subs s_max, s_max, s_inc bhs .Lnext_set /* Next set */ mov pc, lr -END(arm9_icache_sync_all) +END(arm9_icache_sync_range) .Larm9_line_size: .word _C_LABEL(arm_pdcache_line_size) Modified: head/sys/arm/arm/cpufunc_asm_armv5_ec.S ============================================================================== --- head/sys/arm/arm/cpufunc_asm_armv5_ec.S Wed Feb 3 12:11:07 2016 (r295206) +++ head/sys/arm/arm/cpufunc_asm_armv5_ec.S Wed Feb 3 13:47:50 2016 (r295207) @@ -91,9 +91,7 @@ ENTRY_NP(armv5_ec_icache_sync_range) bpl 1b mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ RET -END(armv5_ec_icache_sync_range) -ENTRY_NP(armv5_ec_icache_sync_all) .Larmv5_ec_icache_sync_all: /* * We assume that the code here can never be out of sync with the @@ -109,7 +107,7 @@ ENTRY_NP(armv5_ec_icache_sync_all) bne 1b /* More to do? */ mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */ RET -END(armv5_ec_icache_sync_all) +END(armv5_ec_icache_sync_range) .Larmv5_ec_line_size: .word _C_LABEL(arm_pdcache_line_size) Modified: head/sys/arm/arm/cpufunc_asm_armv7.S ============================================================================== --- head/sys/arm/arm/cpufunc_asm_armv7.S Wed Feb 3 12:11:07 2016 (r295206) +++ head/sys/arm/arm/cpufunc_asm_armv7.S Wed Feb 3 13:47:50 2016 (r295207) @@ -252,16 +252,6 @@ ENTRY(armv7_idcache_wbinv_range) RET END(armv7_idcache_wbinv_range) -ENTRY_NP(armv7_icache_sync_all) -#ifdef SMP - mcr CP15_ICIALLUIS -#else - mcr CP15_ICIALLU -#endif - dsb /* data synchronization barrier */ - isb /* instruction synchronization barrier */ - RET -END(armv7_icache_sync_all) ENTRY_NP(armv7_icache_sync_range) ldr ip, .Larmv7_icache_line_size Modified: head/sys/arm/arm/cpufunc_asm_fa526.S ============================================================================== --- head/sys/arm/arm/cpufunc_asm_fa526.S Wed Feb 3 12:11:07 2016 (r295206) +++ head/sys/arm/arm/cpufunc_asm_fa526.S Wed Feb 3 13:47:50 2016 (r295207) @@ -83,12 +83,6 @@ ENTRY(fa526_idcache_wbinv_all) mov pc, lr END(fa526_idcache_wbinv_all) -ENTRY(fa526_icache_sync_all) - mov r0, #0 - mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ */ - mov pc, lr -END(fa526_icache_sync_all) - ENTRY(fa526_dcache_wbinv_all) mov r0, #0 mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate D$ */ @@ -170,7 +164,7 @@ END(fa526_idcache_wbinv_range) ENTRY(fa526_icache_sync_range) cmp r1, #0x4000 - bhs _C_LABEL(fa526_icache_sync_all) + bhs .Lfa526_icache_sync_all and r2, r0, #(CACHELINE_SIZE - 1) add r1, r1, r2 @@ -184,6 +178,11 @@ ENTRY(fa526_icache_sync_range) 2: mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */ mov pc, lr + +.Lfa526_icache_sync_all: + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 /* invalidate I$ */ + mov pc, lr END(fa526_icache_sync_range) ENTRY(fa526_context_switch) Modified: head/sys/arm/arm/elf_machdep.c ============================================================================== --- head/sys/arm/arm/elf_machdep.c Wed Feb 3 12:11:07 2016 (r295206) +++ head/sys/arm/arm/elf_machdep.c Wed Feb 3 13:47:50 2016 (r295207) @@ -282,7 +282,7 @@ elf_cpu_load_file(linker_file_t lf) #else cpu_dcache_wb_range((vm_offset_t)lf->address, (vm_size_t)lf->size); cpu_l2cache_wb_range((vm_offset_t)lf->address, (vm_size_t)lf->size); - cpu_icache_sync_all(); + cpu_icache_sync_range((vm_offset_t)lf->address, (vm_size_t)lf->size); #endif return (0); } Modified: head/sys/arm/arm/genassym.c ============================================================================== --- head/sys/arm/arm/genassym.c Wed Feb 3 12:11:07 2016 (r295206) +++ head/sys/arm/arm/genassym.c Wed Feb 3 13:47:50 2016 (r295207) @@ -101,7 +101,6 @@ ASSYM(CF_L2CACHE_WB_RANGE, offsetof(stru ASSYM(CF_IDCACHE_WBINV_ALL, offsetof(struct cpu_functions, cf_idcache_wbinv_all)); ASSYM(CF_L2CACHE_WBINV_ALL, offsetof(struct cpu_functions, cf_l2cache_wbinv_all)); ASSYM(CF_TLB_FLUSHID_SE, offsetof(struct cpu_functions, cf_tlb_flushID_SE)); -ASSYM(CF_ICACHE_SYNC, offsetof(struct cpu_functions, cf_icache_sync_all)); ASSYM(V_TRAP, offsetof(struct vmmeter, v_trap)); ASSYM(V_SOFT, offsetof(struct vmmeter, v_soft)); Modified: head/sys/arm/include/cpufunc.h ============================================================================== --- head/sys/arm/include/cpufunc.h Wed Feb 3 12:11:07 2016 (r295206) +++ head/sys/arm/include/cpufunc.h Wed Feb 3 13:47:50 2016 (r295207) @@ -79,7 +79,6 @@ struct cpu_functions { * * We define the following primitives: * - * icache_sync_all Synchronize I-cache * icache_sync_range Synchronize I-cache range * * dcache_wbinv_all Write-back and Invalidate D-cache @@ -104,7 +103,7 @@ struct cpu_functions { * state (such as when it may have lines tagged as valid * that belong to a previous set of mappings). * - * I-cache Synch (all or range): + * I-cache Sync range: * The goal is to synchronize the instruction stream, * so you may beed to write-back dirty D-cache blocks * first. If a range is requested, and you can't @@ -130,7 +129,6 @@ struct cpu_functions { * Valid virtual addresses must be passed to each * cache operation. */ - void (*cf_icache_sync_all) (void); void (*cf_icache_sync_range) (vm_offset_t, vm_size_t); void (*cf_dcache_wbinv_all) (void); @@ -173,7 +171,6 @@ extern u_int cputype; #define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD() #define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e) -#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all() #define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s)) #define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all() @@ -214,7 +211,6 @@ void fa526_context_switch (void); void fa526_cpu_sleep (int); void fa526_tlb_flushID_SE (u_int); -void fa526_icache_sync_all (void); void fa526_icache_sync_range(vm_offset_t start, vm_size_t end); void fa526_dcache_wbinv_all (void); void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end); @@ -231,8 +227,7 @@ void arm9_tlb_flushID_SE (u_int va); void arm9_context_switch (void); #endif -#if defined(CPU_ARM9) -void arm9_icache_sync_all (void); +#if defined(CPU_ARM9) void arm9_icache_sync_range (vm_offset_t, vm_size_t); void arm9_dcache_wbinv_all (void); @@ -275,7 +270,6 @@ void armv6_idcache_wbinv_all (void); void armv7_setttb (u_int); void armv7_tlb_flushID (void); void armv7_tlb_flushID_SE (u_int); -void armv7_icache_sync_all (void); void armv7_icache_sync_range (vm_offset_t, vm_size_t); void armv7_idcache_wbinv_range (vm_offset_t, vm_size_t); void armv7_idcache_inv_all (void); @@ -319,7 +313,6 @@ void armv6_idcache_inv_all (void); void arm11x6_setttb (u_int); void arm11x6_idcache_wbinv_all (void); void arm11x6_dcache_wbinv_all (void); -void arm11x6_icache_sync_all (void); void arm11x6_icache_sync_range (vm_offset_t, vm_size_t); void arm11x6_idcache_wbinv_range (vm_offset_t, vm_size_t); void arm11x6_setup (void); @@ -329,7 +322,6 @@ void arm11x6_sleep #if defined(CPU_ARM9E) void armv5_ec_setttb(u_int); -void armv5_ec_icache_sync_all(void); void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t); void armv5_ec_dcache_wbinv_all(void);
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