Date: Tue, 22 Oct 2013 15:45:31 +0000 (UTC) From: Brooks Davis <brooks@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r256912 - in head/sys: boot/fdt/dts mips/conf Message-ID: <201310221545.r9MFjVWi083110@svn.freebsd.org>
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Author: brooks Date: Tue Oct 22 15:45:31 2013 New Revision: 256912 URL: http://svnweb.freebsd.org/changeset/base/256912 Log: Sync BERI kernel configs with P4: Switch the majority of device configuration to FDT from hints. Add BERI_*_BASE configs to reduce duplication in the MDROOT and SDROOT kernels. Add NFS and GSSAPI support by default. MFC after: 3 days Sponsored by: DARPA/AFRL Added: head/sys/boot/fdt/dts/beri-sim.dts (contents, props changed) head/sys/boot/fdt/dts/beripad-de4.dts (contents, props changed) head/sys/mips/conf/BERI_DE4_BASE (contents, props changed) head/sys/mips/conf/BERI_SIM_BASE (contents, props changed) head/sys/mips/conf/BERI_SIM_SDROOT (contents, props changed) Modified: head/sys/mips/conf/BERI_DE4.hints head/sys/mips/conf/BERI_DE4_MDROOT head/sys/mips/conf/BERI_DE4_SDROOT head/sys/mips/conf/BERI_SIM_MDROOT head/sys/mips/conf/BERI_TEMPLATE Added: head/sys/boot/fdt/dts/beri-sim.dts ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/boot/fdt/dts/beri-sim.dts Tue Oct 22 15:45:31 2013 (r256912) @@ -0,0 +1,144 @@ +/*- + * Copyright (c) 2012-2013 Robert N. M. Watson + * Copyright (c) 2013 SRI International + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) + * ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/dts-v1/; + +/* + * Device names here have been largely made up on the spot, especially for the + * "compatible" strings, and might want to be revised. + * + * For now, use 32-bit addressing as our Avalon bus is 32-bit. However, in + * the future, we should likely change to 64-bit. + */ + +/ { + model = "SRI/Cambridge BERI simulation"; + compatible = "sri-cambridge,beri-sim"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <1>; + + /* + * Secondary CPUs all start disabled and use the + * spin-table enable method. cpu-release-addr must be + * specified for each cpu other than cpu@0. Values of + * cpu-release-addr grow down from 0x100000 (kernel). + */ + status = "disabled"; + enable-method = "spin-table"; + + cpu@0 { + device-type = "cpu"; + compatible = "sri-cambridge,beri"; + + reg = <0>; + status = "okay"; + }; + +/* + cpu@1 { + device-type = "cpu"; + compatible = "sri-cambridge,beri"; + + reg = <1>; + // XXX: should we need cached prefix? + cpu-release-addr = <0xffffffff 0x800fffe0>; + }; +*/ + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + + /* + * Declare mips,mips4k since BERI doesn't (yet) have a PIC, so + * we use mips4k coprocessor 0 interrupt management directly. + */ + compatible = "simple-bus", "mips,mips4k"; + ranges = <>; + + memory { + device_type = "memory"; + reg = <0x0 0x4000000>; // 64M at 0x0 + }; + + beripic: beripic@7f804000 { + compatible = "sri-cambridge,beri-pic"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x7f804000 0x400 + 0x7f806000 0x10 + 0x7f806080 0x10 + 0x7f806100 0x10>; + interrupts = <0 1 2 3 4>; + hard-interrupt-sources = <64>; + soft-interrupt-sources = <64>; + }; + + serial@7f000000 { + compatible = "altera,jtag_uart-11_0"; + reg = <0x7f000000 0x40>; + interrupts = <0>; + interrupt-parent = <&beripic>; + }; + + serial@7f001000 { + compatible = "altera,jtag_uart-11_0"; + reg = <0x7f001000 0x40>; + }; + + serial@7f002000 { + compatible = "altera,jtag_uart-11_0"; + reg = <0x7f002000 0x40>; + }; + + sdcard@7f008000 { + compatible = "altera,sdcard_11_2011"; + reg = <0x7f008000 0x400>; + }; + + avgen@0x7f00a000 { + compatible = "sri-cambridge,avgen"; + reg = <0x7f00a000 0x14>; + sri-cambridge,width = <4>; + sri-cambridge,fileio = "rw"; + sri-cambridge,devname = "berirom"; + }; + }; +}; Added: head/sys/boot/fdt/dts/beripad-de4.dts ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/boot/fdt/dts/beripad-de4.dts Tue Oct 22 15:45:31 2013 (r256912) @@ -0,0 +1,266 @@ +/*- + * Copyright (c) 2012-2013 Robert N. M. Watson + * Copyright (c) 2013 SRI International + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) + * ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +/dts-v1/; + +/* + * Device names here have been largely made up on the spot, especially for the + * "compatible" strings, and might want to be revised. + * + * For now, use 32-bit addressing as our Avalon bus is 32-bit. However, in + * the future, we should likely change to 64-bit. + */ + +/ { + model = "SRI/Cambridge BeriPad (DE4)"; + compatible = "sri-cambridge,beripad-de4"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <1>; + + /* + * Secondary CPUs all start disabled and use the + * spin-table enable method. cpu-release-addr must be + * specified for each cpu other than cpu@0. Values of + * cpu-release-addr grow down from 0x100000 (kernel). + */ + status = "disabled"; + enable-method = "spin-table"; + + cpu@0 { + device-type = "cpu"; + compatible = "sri-cambridge,beri"; + + reg = <0>; + status = "okay"; + }; + +/* + cpu@1 { + device-type = "cpu"; + compatible = "sri-cambridge,beri"; + + reg = <1>; + // XXX: should we need cached prefix? + cpu-release-addr = <0xffffffff 0x800fffe0>; + }; +*/ + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + #interrupt-cells = <1>; + + /* + * Declare mips,mips4k since BERI doesn't (yet) have a PIC, so + * we use mips4k coprocessor 0 interrupt management directly. + */ + compatible = "simple-bus", "mips,mips4k"; + ranges = <>; + + memory { + device_type = "memory"; + reg = <0x0 0x40000000>; // 1G at 0x0 + }; + + beripic: beripic@7f804000 { + compatible = "sri-cambridge,beri-pic"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x7f804000 0x400 + 0x7f806000 0x10 + 0x7f806080 0x10 + 0x7f806100 0x10>; + interrupts = <0 1 2 3 4>; + hard-interrupt-sources = <64>; + soft-interrupt-sources = <64>; + }; + + serial@7f002100 { + compatible = "ns16550"; + reg = <0x7f002100 0x20>; + reg-shift = <2>; + clock-frequency = <50000000>; + interrupts = <6>; + interrupt-parent = <&beripic>; + }; + + serial@7f000000 { + compatible = "altera,jtag_uart-11_0"; + reg = <0x7f000000 0x40>; + interrupts = <0>; + interrupt-parent = <&beripic>; + }; + + serial@7f001000 { + compatible = "altera,jtag_uart-11_0"; + reg = <0x7f001000 0x40>; + }; + + serial@7f002000 { + compatible = "altera,jtag_uart-11_0"; + reg = <0x7f002000 0x40>; + }; + + sdcard@7f008000 { + compatible = "altera,sdcard_11_2011"; + reg = <0x7f008000 0x400>; + }; + + led@7f006000 { + compatible = "sri-cambridge,de4led"; + reg = <0x7f006000 0x1>; + }; + + /* + * XXX-BZ keep flash before ethernet so that atse can read the + * Ethernet addresses for now. + */ + flash@74000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x74000000 0x4000000>; + + /* Board configuration */ + partition@0 { + reg = <0x0 0x20000>; + label = "config"; + }; + + /* Power up FPGA image */ + partition@20000 { + reg = <0x20000 0xc00000>; + label = "fpga0"; + }; + + /* Secondary FPGA image (on RE_CONFIGn button) */ + partition@C20000 { + reg = <0xc20000 0xc00000>; + label = "fpga1"; + }; + + /* Space for operating system use */ + partition@1820000 { + reg = <0x1820000 0x027c0000>; + label = "os"; + }; + + /* Second stage bootloader */ + parition@3fe0000 { + reg = <0x3fe0000 0x20000>; + label = "boot"; + }; + }; + + ethernet@7f007000 { + compatible = "altera,atse"; + // MAC, RX+RXC, TX+TXC. + reg = <0x7f007000 0x400 + 0x7f007500 0x8 + 0x7f007520 0x20 + 0x7f007400 0x8 + 0x7f007420 0x20>; + // RX, TX + interrupts = <1 2>; + interrupt-parent = <&beripic>; + }; + + ethernet@7f005000 { + compatible = "altera,atse"; + // MAC, RX+RXC, TX+TXC. + reg = <0x7f005000 0x400 + 0x7f005500 0x8 + 0x7f005520 0x20 + 0x7f005400 0x8 + 0x7f005420 0x20>; + // RX, TX + interrupts = <11 12>; + interrupt-parent = <&beripic>; + }; + + touchscreen@70400000 { + compatible = "sri-cambridge,mtl"; + reg = <0x70400000 0x1000 + 0x70000000 0x177000 + 0x70177000 0x2000>; + }; + + usb@0x7f100000 { + compatible = "philips,isp1761"; + reg = <0x7f100000 0x40000 + 0x7f140000 0x4>; + // IRQ 4 is DC, IRQ 5 is HC. + interrupts = <4 5>; + interrupt-parent = <&beripic>; + }; + + avgen@0x7f009000 { + compatible = "sri-cambridge,avgen"; + reg = <0x7f009000 0x2>; + sri-cambridge,width = <1>; + sri-cambridge,fileio = "r"; + sri-cambridge,devname = "de4bsw"; + }; + + avgen@0x7f00a000 { + compatible = "sri-cambridge,avgen"; + reg = <0x7f00a000 0x14>; + sri-cambridge,width = <4>; + sri-cambridge,fileio = "rw"; + sri-cambridge,devname = "berirom"; + }; + + avgen@0x7f00c000 { + compatible = "sri-cambridge,avgen"; + reg = <0x7f00c000 0x8>; + sri-cambridge,width = <4>; + sri-cambridge,fileio = "rw"; + sri-cambridge,devname = "de4tempfan"; + }; + + avgen@0x7f100000 { + compatible = "sri-cambridge,avgen"; + reg = <0x7f100000 0x40000>; + sri-cambridge,width = <4>; + sri-cambridge,fileio = "r"; + sri-cambridge,devname = "usbmem"; + }; + + }; +}; Modified: head/sys/mips/conf/BERI_DE4.hints ============================================================================== --- head/sys/mips/conf/BERI_DE4.hints Tue Oct 22 15:29:59 2013 (r256911) +++ head/sys/mips/conf/BERI_DE4.hints Tue Oct 22 15:45:31 2013 (r256912) @@ -1,75 +1,26 @@ # $FreeBSD$ -# -# Altera JTAG UARTs configured for console, debugging, and data putput on the -# Terasic DE-4. -# -hint.altera_jtag_uart.0.at="nexus0" -hint.altera_jtag_uart.0.maddr=0x7f000000 -hint.altera_jtag_uart.0.msize=0x40 -hint.altera_jtag_uart.0.irq=0 +# Hardwired location of bitfile +hint.map.0.at="cfid0s.fpga0" +hint.map.0.start=0x00000000 +hint.map.0.end=0x00c00000 +hint.map.0.name="fpga" + +# Kernel on the second chip +hint.map.1.at="cfid0s.os" +hint.map.1.start=0x007e0000 +hint.map.1.end=0x01fe0000 +hint.map.1.name="kernel" + +# Altera Triple-Speed Ethernet Mac, present in tPad and DE-4 configurations +# configured from fdt(4) but PHYs are still described in here. +# Currently configured for individual tse_mac cores. +hint.e1000phy.0.at="miibus0" +hint.e1000phy.0.phyno=0 +hint.e1000phy.1.at="miibus0" +hint.e1000phy.1.phyno=0 +hint.e1000phy.2.at="miibus0" +hint.e1000phy.2.phyno=0 +hint.e1000phy.3.at="miibus0" +hint.e1000phy.3.phyno=0 -hint.altera_jtag_uart.1.at="nexus0" -hint.altera_jtag_uart.1.maddr=0x7f001000 -hint.altera_jtag_uart.1.msize=0x40 - -hint.altera_jtag_uart.2.at="nexus0" -hint.altera_jtag_uart.2.maddr=0x7f002000 -hint.altera_jtag_uart.2.msize=0x40 - -# -# On-board DE4 and tPad SD Card IP core -# -hint.altera_sdcardc.0.at="nexus0" -hint.altera_sdcardc.0.maddr=0x7f008000 -hint.altera_sdcardc.0.msize=0x400 - -# -# On-board DE4 8-element LED -# -hint.terasic_de4led.0.at="nexus0" -hint.terasic_de4led.0.maddr=0x7f006000 -hint.terasic_de4led.0.msize=1 -hint.terasic_de4led.0.de4led_0_cmd="f9" - -# -# Terasic Multi-touch LCD (MTL), an optional feature in DE-4 configurations. -# -hint.terasic_mtl.0.at="nexus0" -hint.terasic_mtl.0.reg_maddr=0x70400000 -hint.terasic_mtl.0.reg_msize=0x1000 -hint.terasic_mtl.0.pixel_maddr=0x70000000 -hint.terasic_mtl.0.pixel_msize=0x177000 -hint.terasic_mtl.0.text_maddr=0x70177000 -hint.terasic_mtl.0.text_msize=0x2000 - -# -# BERI Hardware Version ROM -# -hint.altera_avgen.0.at="nexus0" -hint.altera_avgen.0.maddr=0x7F00A000 -hint.altera_avgen.0.msize=20 -hint.altera_avgen.0.width=4 -hint.altera_avgen.0.fileio="rw" -hint.altera_avgen.0.devname="berirom" - -# -# Expose the DE4 flash via an Avalon "generic" device. -# -#hint.altera_avgen.0.at="nexus0" -#hint.altera_avgen.0.maddr=0x74000000 -#hint.altera_avgen.0.msize=0x4000000 -#hint.altera_avgen.0.width=2 -#hint.altera_avgen.0.fileio="rw" -#hint.altera_avgen.0.mmapio="rwx" -#hint.altera_avgen.0.devname="de4flash" - -# -# Expose the DE4 buttons and switches via an Avalon "generic" device. -# -hint.altera_avgen.0.at="nexus0" -hint.altera_avgen.0.maddr=0x7f009000 -hint.altera_avgen.0.msize=2 -hint.altera_avgen.0.width=1 -hint.altera_avgen.0.fileio="r" -hint.altera_avgen.0.devname="de4bsw" Added: head/sys/mips/conf/BERI_DE4_BASE ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/mips/conf/BERI_DE4_BASE Tue Oct 22 15:45:31 2013 (r256912) @@ -0,0 +1,41 @@ +# +# BERI_DE4_BASE -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible RISC +# Implementation) FPGA soft core, as configured in its Terasic DE-4 reference +# configuration. This kernel configration must be further specialized to +# to include a root filesystem specification. +# +# $FreeBSD$ +# + +include "BERI_TEMPLATE" + +ident BERI_DE4_BASE + +options NFSCL # New Network Filesystem Client +options NFSLOCKD # Network Lock Manager +options NFS_ROOT # NFS usable as /, requires NFSCL + +options FDT +options FDT_DTB_STATIC +makeoptions FDT_DTS_FILE=beripad-de4.dts + +hints "BERI_DE4.hints" # Flash partitions still use hints. + +device altera_atse +device altera_avgen +device altera_jtag_uart +device altera_sdcard +device terasic_de4led +device terasic_mtl + +device bpf +device cfi +device cfid +options CFI_SUPPORT_STRATAFLASH +device sc + +device uart + +device miibus +options DEVICE_POLLING + Modified: head/sys/mips/conf/BERI_DE4_MDROOT ============================================================================== --- head/sys/mips/conf/BERI_DE4_MDROOT Tue Oct 22 15:29:59 2013 (r256911) +++ head/sys/mips/conf/BERI_DE4_MDROOT Tue Oct 22 15:45:31 2013 (r256912) @@ -1,29 +1,19 @@ # -# BERI_DE4 -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible RISC -# Implementation) FPGA soft core, as configured in its Terasic DE-4 reference -# configuration. +# BERI_DE4_MDROOT -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible +# RISC # Implementation) FPGA soft core, as configured in its Terasic DE-4 +# reference configuration. # # $FreeBSD$ # -include "BERI_TEMPLATE" +include "BERI_DE4_BASE" ident BERI_DE4_MDROOT -hints "BERI_DE4.hints" #Default places to look for devices. - # # This kernel configuration uses an embedded 8MB memory root file system. # Adjust the following path based on local requirements. # options MD_ROOT # MD is a potential root device -options MD_ROOT_SIZE=8192 +options MD_ROOT_SIZE=26112 # 25.5MB options ROOTDEVNAME=\"ufs:md0\" - -device altera_avgen -device altera_jtag_uart -device altera_sdcard -device terasic_de4led -device terasic_mtl - -device sc Modified: head/sys/mips/conf/BERI_DE4_SDROOT ============================================================================== --- head/sys/mips/conf/BERI_DE4_SDROOT Tue Oct 22 15:29:59 2013 (r256911) +++ head/sys/mips/conf/BERI_DE4_SDROOT Tue Oct 22 15:45:31 2013 (r256912) @@ -1,23 +1,16 @@ # -# BERI_DE4 -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible RISC -# Implementation) FPGA soft core, as configured in its Terasic DE-4 reference -# configuration. +# BERI_DE4_SDROOT -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible +# RISC Implementation) FPGA soft core, as configured in its Terasic DE-4 +# reference configuration. # # $FreeBSD$ # -include "BERI_TEMPLATE" +include "BERI_DE4_BASE" ident BERI_DE4_SDROOT -hints "BERI_DE4.hints" #Default places to look for devices. - -options ROOTDEVNAME=\"ufs:altera_sdcard0\" - -device altera_avgen -device altera_jtag_uart -device altera_sdcard -device terasic_de4led -device terasic_mtl - -device sc +# +# This kernel expects to find its root filesystem on the SD Card. +# +options ROOTDEVNAME=\"ufs:/dev/altera_sdcard0\" Added: head/sys/mips/conf/BERI_SIM_BASE ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/mips/conf/BERI_SIM_BASE Tue Oct 22 15:45:31 2013 (r256912) @@ -0,0 +1,19 @@ +# +# BERI_SIM_BASE -- Base kernel for the SRI/Cambridge "BERI" (Bluespec +# Extensible RISC Implementation) FPGA soft core, as configured for +# simulation. +# +# $FreeBSD$ +# + +include "BERI_TEMPLATE" + +options FDT +options FDT_DTB_STATIC +makeoptions FDT_DTS_FILE=beri-sim.dts + +options ALTERA_SDCARD_FAST_SIM + +device altera_avgen +device altera_jtag_uart +device altera_sdcard Modified: head/sys/mips/conf/BERI_SIM_MDROOT ============================================================================== --- head/sys/mips/conf/BERI_SIM_MDROOT Tue Oct 22 15:29:59 2013 (r256911) +++ head/sys/mips/conf/BERI_SIM_MDROOT Tue Oct 22 15:45:31 2013 (r256912) @@ -1,24 +1,18 @@ # -# BERI_SIM -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible RISC -# Implementation) FPGA soft core, as configured for simulation. +# BERI_SIM_MDROOT -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible +# RISC Implementation) FPGA soft core, as configured for simulation. # # $FreeBSD$ # -include "BERI_TEMPLATE" +include "BERI_SIM_BASE" ident BERI_SIM_MDROOT -hints "BERI_SIM.hints" #Default places to look for devices. - # -# This kernel configuration uses an embedded 8MB memory root file system. +# This kernel configuration uses an embedded memory root file system. # Adjust the following path based on local requirements. # options MD_ROOT # MD is a potential root device -options MD_ROOT_SIZE=8192 +options MD_ROOT_SIZE=26112 # 25.5MB options ROOTDEVNAME=\"ufs:md0\" - -device altera_avgen -device altera_jtag_uart -device altera_sdcard Added: head/sys/mips/conf/BERI_SIM_SDROOT ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ head/sys/mips/conf/BERI_SIM_SDROOT Tue Oct 22 15:45:31 2013 (r256912) @@ -0,0 +1,15 @@ +# +# BERI_SIM_SDROOT -- Kernel for the SRI/Cambridge "BERI" (Bluespec Extensible +# RISC Implementation) FPGA soft core, as configured for simulation. +# +# $FreeBSD$ +# + +include "BERI_SIM_BASE" + +ident BERI_SIM_SDROOT + +# +# This kernel expects to find its root filesystem on the SD Card. +# +options ROOTDEVNAME=\"ufs:/dev/altera_sdcard0\" Modified: head/sys/mips/conf/BERI_TEMPLATE ============================================================================== --- head/sys/mips/conf/BERI_TEMPLATE Tue Oct 22 15:29:59 2013 (r256911) +++ head/sys/mips/conf/BERI_TEMPLATE Tue Oct 22 15:45:31 2013 (r256912) @@ -39,7 +39,9 @@ options FFS #Berkeley Fast Filesystem options INET options INET6 +options KGSSAPI options NFSCL +options NFSLOCKD options NFS_ROOT # Debugging for use in -current @@ -49,10 +51,11 @@ options INVARIANT_SUPPORT #Extra sanity #options WITNESS #Enable checks to detect deadlocks and cycles #options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed -device geom_map - -device md +device crypto +device cryptodev device ether +device geom_map device loop +device md device random device snp
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