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Date:      Tue, 18 Jul 2000 15:47:27 -0600
From:      "Justin T. Gibbs" <gibbs@plutotech.com>
To:        =?ISO-8859-1?Q?G=E9rard_Roudier?= <groudier@club-internet.fr>
Cc:        mjacob@feral.com, cvs-committers@FreeBSD.org, cvs-all@FreeBSD.org
Subject:   Re: cvs commit: src/sys/cam cam_ccb.h cam_xpt.c src/sys/cam/scsi scsi_all.c scsi_message.h src/sys/dev/aic7xxx aicasm_insformat.h 93cx6.c 93cx6.h ahc_eisa.c ahc_pci.c aic7xxx.c aic7xxx.h aic7xxx.reg aic7xxx.seq aicasm.c aicasm.h aicasm_gram.y ... 
Message-ID:  <200007182146.PAA56521@pluto.plutotech.com>
In-Reply-To: Your message of "Tue, 18 Jul 2000 23:09:56 %2B0200." <Pine.LNX.4.10.10007182242190.1928-100000@linux.local> 

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>
>
>First, thanks for your commit. I will look into and steal any good idea =

>from you I will found. :-)

This doesn't change the CAM API for SIMs.  I basically lopped off the
new SET/GET transfer settings from my latest driver and faked the rest
of the driver out.  Its not perfect, but it will do until the API
is changed.

>> I'm hoping that being able to address 512GB will be enough
>> for a while.  I'd rather not expand the size of the S/G list
>> members for address space no-one will be touching for the
>> foreseeable future.
>
>This does not seem so simple.
>Most systems I read about that allow 64 bit addressing from the PCI BUS =

>require some high address bits beyond bit 39 to be set in the address =

>for the bridge to understand 64 bit DMA adressing.

Well, for systems where a full 64bits are required for their "bus dma"
implementation, I'll just have to bite the bullet and expand the S/G
list format.  The chips do support a full 8byte address, I just didn't
want to pay the full space price (including in the S/G prefetch buffer
on the chip) on all systems.

>Hmmm... Intel PAE Painful Address Extension seems simple compared to =

>32 bit PCI chips extended to 64 bit PCI addressing.

It seems that this is only the case for architectures that do not
map physical =3D=3D pci address space.

--
Justin



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