Date: Fri, 22 Dec 2017 23:27:03 +0000 (UTC) From: Konstantin Belousov <kib@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r327097 - in head/sys/mips: include mips Message-ID: <201712222327.vBMNR3w7002893@repo.freebsd.org>
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Author: kib Date: Fri Dec 22 23:27:03 2017 New Revision: 327097 URL: https://svnweb.freebsd.org/changeset/base/327097 Log: Remove mips MD atomic_load_64 and atomic_store_64. The only users of the functions were db_read_bytes() and db_write_bytes() ddb(4) interfaces. Replace the calls with direct reads and writes, which are automatically atomic on 64bits and n32. Note that removed assembler implementation for mips32 is not atomic anyway. Reviewed by: jhb Discussed with: imp Sponsored by: The FreeBSD Foundation MFC after: 1 week Differential revision: https://reviews.freebsd.org/D13586 Modified: head/sys/mips/include/atomic.h head/sys/mips/mips/db_interface.c head/sys/mips/mips/support.S Modified: head/sys/mips/include/atomic.h ============================================================================== --- head/sys/mips/include/atomic.h Fri Dec 22 21:54:39 2017 (r327096) +++ head/sys/mips/include/atomic.h Fri Dec 22 23:27:03 2017 (r327097) @@ -341,24 +341,6 @@ atomic_store_rel_##WIDTH(__volatile uint##WIDTH##_t *p ATOMIC_STORE_LOAD(32) ATOMIC_STORE_LOAD(64) -#if !defined(__mips_n64) && !defined(__mips_n32) -void atomic_store_64(__volatile uint64_t *, uint64_t); -uint64_t atomic_load_64(__volatile uint64_t *); -#elif defined (__mips_n32) -static __inline void -atomic_store_64(__volatile uint64_t *p, uint64_t v) -{ - *p = v; -} - -static __inline uint64_t -atomic_load_64(__volatile uint64_t *p) -{ - return (*p); -} -/* #else atomic_common.h definitions of atomic_load/store_64 are used */ -#endif - #undef ATOMIC_STORE_LOAD /* Modified: head/sys/mips/mips/db_interface.c ============================================================================== --- head/sys/mips/mips/db_interface.c Fri Dec 22 21:54:39 2017 (r327096) +++ head/sys/mips/mips/db_interface.c Fri Dec 22 23:27:03 2017 (r327097) @@ -152,6 +152,7 @@ db_read_bytes(vm_offset_t addr, size_t size, char *dat /* * 'addr' could be a memory-mapped I/O address. Try to * do atomic load/store in unit of size requested. + * size == 8 is only atomic on 64bit or n32 kernel. */ if ((size == 2 || size == 4 || size == 8) && ((addr & (size -1)) == 0) && @@ -164,8 +165,7 @@ db_read_bytes(vm_offset_t addr, size_t size, char *dat *(uint32_t *)data = *(uint32_t *)addr; break; case 8: - *(uint64_t *)data = atomic_load_64( - (void *)addr); + *(uint64_t *)data = *(uint64_t *)addr; break; } } else { @@ -195,6 +195,7 @@ db_write_bytes(vm_offset_t addr, size_t size, char *da /* * 'addr' could be a memory-mapped I/O address. Try to * do atomic load/store in unit of size requested. + * size == 8 is only atomic on 64bit or n32 kernel. */ if ((size == 2 || size == 4 || size == 8) && ((addr & (size -1)) == 0) && @@ -207,8 +208,7 @@ db_write_bytes(vm_offset_t addr, size_t size, char *da *(uint32_t *)addr = *(uint32_t *)data; break; case 8: - atomic_store_64((uint64_t *)addr, - *(uint64_t *)data); + *(uint64_t *)addr = *(uint64_t *)data; break; } } else { Modified: head/sys/mips/mips/support.S ============================================================================== --- head/sys/mips/mips/support.S Fri Dec 22 21:54:39 2017 (r327096) +++ head/sys/mips/mips/support.S Fri Dec 22 23:27:03 2017 (r327097) @@ -839,74 +839,7 @@ LEAF(atomic_subtract_8) nop END(atomic_subtract_8) -/* - * atomic 64-bit register read/write assembly language support routines. - */ - .set noreorder # Noreorder is default style! - -#if !defined(__mips_n64) && !defined(__mips_n32) - /* - * I don't know if these routines have the right number of - * NOPs in it for all processors. XXX - * - * Maybe it would be better to just leave this undefined in that case. - * - * XXX These routines are not safe in the case of a TLB miss on a1 or - * a0 unless the trapframe is 64-bit, which it just isn't with O32. - * If we take any exception, not just an interrupt, the upper - * 32-bits will be clobbered. Use only N32 and N64 kernels if you - * want to use 64-bit registers while interrupts are enabled or - * with memory operations. Since this isn't even using load-linked - * and store-conditional, perhaps it should just use two registers - * instead, as is right and good with the O32 ABI. - */ -LEAF(atomic_store_64) - mfc0 t1, MIPS_COP_0_STATUS - and t2, t1, ~MIPS_SR_INT_IE - mtc0 t2, MIPS_COP_0_STATUS - nop - nop - nop - nop - ld t0, (a1) - nop - nop - sd t0, (a0) - nop - nop - mtc0 t1,MIPS_COP_0_STATUS - nop - nop - nop - nop - j ra - nop -END(atomic_store_64) - -LEAF(atomic_load_64) - mfc0 t1, MIPS_COP_0_STATUS - and t2, t1, ~MIPS_SR_INT_IE - mtc0 t2, MIPS_COP_0_STATUS - nop - nop - nop - nop - ld t0, (a0) - nop - nop - sd t0, (a1) - nop - nop - mtc0 t1,MIPS_COP_0_STATUS - nop - nop - nop - nop - j ra - nop -END(atomic_load_64) -#endif #if defined(DDB) || defined(DEBUG)
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