Date: Wed, 20 Feb 2008 17:59:49 GMT From: "Randall R. Stewart" <rrs@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 135808 for review Message-ID: <200802201759.m1KHxnaI075638@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=135808 Change 135808 by rrs@rrs-mips2-jnpr on 2008/02/20 17:59:08 s9indent. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/mips/include/cpu.h#11 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/mips/include/cpu.h#11 (text+ko) ==== @@ -349,25 +349,25 @@ * CPU identification, from PRID register. */ union cpuprid { - int cpuprid; + int cpuprid; struct { #if BYTE_ORDER == BIG_ENDIAN - u_int pad1:8; /* reserved */ - u_int cp_vendor:8; /* company identifier */ - u_int cp_imp:8; /* implementation identifier */ - u_int cp_majrev:4; /* major revision identifier */ - u_int cp_minrev:4; /* minor revision identifier */ + u_int pad1:8; /* reserved */ + u_int cp_vendor:8; /* company identifier */ + u_int cp_imp:8; /* implementation identifier */ + u_int cp_majrev:4; /* major revision identifier */ + u_int cp_minrev:4; /* minor revision identifier */ #else - u_int cp_minrev:4; /* minor revision identifier */ - u_int cp_majrev:4; /* major revision identifier */ - u_int cp_imp:8; /* implementation identifier */ - u_int cp_vendor:8; /* company identifier */ - u_int pad1:8; /* reserved */ + u_int cp_minrev:4; /* minor revision identifier */ + u_int cp_majrev:4; /* major revision identifier */ + u_int cp_imp:8; /* implementation identifier */ + u_int cp_vendor:8; /* company identifier */ + u_int pad1:8; /* reserved */ #endif - } cpu; + } cpu; }; -#endif /* !_LOCORE */ +#endif /* !_LOCORE */ /* * CTL_MACHDEP definitions. @@ -391,87 +391,88 @@ /* * MIPS CPU types (cp_imp). */ -#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */ -#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */ -#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */ -#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */ -#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */ -#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */ -#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */ -#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */ -#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */ -#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */ -#define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */ -#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ -#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ -#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ -#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */ -#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */ -#define MIPS_RM7000 0x27 /* QED RM7000 CPU ISA IV */ -#define MIPS_RM52X0 0x28 /* QED RM52X0 CPU ISA IV */ -#define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */ -#define MIPS_RM9000 0x34 /* E9000 CPU */ +#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */ +#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */ +#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */ +#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */ +#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */ +#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */ +#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */ +#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */ +#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */ +#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */ +#define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */ +#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ +#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ +#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ +#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */ +#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */ +#define MIPS_RM7000 0x27 /* QED RM7000 CPU ISA IV */ +#define MIPS_RM52X0 0x28 /* QED RM52X0 CPU ISA IV */ +#define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */ +#define MIPS_RM9000 0x34 /* E9000 CPU */ /* * MIPS FPU types */ -#define MIPS_SOFT 0x00 /* Software emulation ISA I */ -#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ -#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ -#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ -#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ -#define MIPS_R4010 0x05 /* MIPS R4000/R4400 FPC ISA II */ -#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ -#define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */ -#define MIPS_R4210 0x0a /* MIPS R4200 FPC (ICE) ISA III */ -#define MIPS_UNKF1 0x0b /* unnanounced product cpu ISA III */ -#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ -#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ -#define MIPS_R3SONY 0x21 /* Sony R3000 based FPU ISA I */ -#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ -#define MIPS_R5010 0x23 /* MIPS R5000 based FPU ISA IV */ -#define MIPS_RM7000 0x27 /* QED RM7000 FPU ISA IV */ -#define MIPS_RM5230 0x28 /* QED RM52X0 based FPU ISA IV */ -#define MIPS_RM52XX 0x28 /* QED RM52X0 based FPU ISA IV */ -#define MIPS_VR5400 0x54 /* NEC Vr5400 FPU ISA IV+ */ +#define MIPS_SOFT 0x00 /* Software emulation ISA I */ +#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ +#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ +#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ +#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ +#define MIPS_R4010 0x05 /* MIPS R4000/R4400 FPC ISA II */ +#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ +#define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */ +#define MIPS_R4210 0x0a /* MIPS R4200 FPC (ICE) ISA III */ +#define MIPS_UNKF1 0x0b /* unnanounced product cpu ISA III */ +#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ +#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ +#define MIPS_R3SONY 0x21 /* Sony R3000 based FPU ISA I */ +#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ +#define MIPS_R5010 0x23 /* MIPS R5000 based FPU ISA IV */ +#define MIPS_RM7000 0x27 /* QED RM7000 FPU ISA IV */ +#define MIPS_RM5230 0x28 /* QED RM52X0 based FPU ISA IV */ +#define MIPS_RM52XX 0x28 /* QED RM52X0 based FPU ISA IV */ +#define MIPS_VR5400 0x54 /* NEC Vr5400 FPU ISA IV+ */ #ifndef _LOCORE -extern union cpuprid cpu_id; +extern union cpuprid cpu_id; + #define mips_proc_type() ((cpu_id.cpu.cp_vendor << 8) | cpu_id.cpu.cp_imp) #define mips_set_proc_type(type) (cpu_id.cpu.cp_vendor = (type) >> 8, \ cpu_id.cpu.cp_imp = ((type) & 0x00ff)) -#endif /* !_LOCORE */ +#endif /* !_LOCORE */ #if defined(_KERNEL) && !defined(_LOCORE) -extern union cpuprid fpu_id; +extern union cpuprid fpu_id; struct tlb; struct user; u_int32_t mips_cp0_config1_read(void); -int Mips_ConfigCache(void); -void Mips_SetWIRED(int); -void Mips_SetPID(int); -u_int Mips_GetCOUNT(void); -void Mips_SetCOMPARE(u_int); -u_int Mips_GetCOMPARE(void); +int Mips_ConfigCache(void); +void Mips_SetWIRED(int); +void Mips_SetPID(int); +u_int Mips_GetCOUNT(void); +void Mips_SetCOMPARE(u_int); +u_int Mips_GetCOMPARE(void); -void Mips_SyncCache(void); -void Mips_SyncDCache(vm_offset_t, int); -void Mips_HitSyncDCache(vm_offset_t, int); -void Mips_HitSyncSCache(vm_offset_t, int); -void Mips_IOSyncDCache(vm_offset_t, int, int); -void Mips_HitInvalidateDCache(vm_offset_t, int); -void Mips_SyncICache(vm_offset_t, int); -void Mips_InvalidateICache(vm_offset_t, int); +void Mips_SyncCache(void); +void Mips_SyncDCache(vm_offset_t, int); +void Mips_HitSyncDCache(vm_offset_t, int); +void Mips_HitSyncSCache(vm_offset_t, int); +void Mips_IOSyncDCache(vm_offset_t, int, int); +void Mips_HitInvalidateDCache(vm_offset_t, int); +void Mips_SyncICache(vm_offset_t, int); +void Mips_InvalidateICache(vm_offset_t, int); -void Mips_TLBFlush(int); -void Mips_TLBFlushAddr(vm_offset_t); -void Mips_TLBWriteIndexed(int, struct tlb *); -void Mips_TLBUpdate(vm_offset_t, unsigned); -void Mips_TLBRead(int, struct tlb *); -void mips_TBIAP(int); -void wbflush(void); +void Mips_TLBFlush(int); +void Mips_TLBFlushAddr(vm_offset_t); +void Mips_TLBWriteIndexed(int, struct tlb *); +void Mips_TLBUpdate(vm_offset_t, unsigned); +void Mips_TLBRead(int, struct tlb *); +void mips_TBIAP(int); +void wbflush(void); extern u_int32_t cpu_counter_interval; /* Number of counter ticks/tick */ extern u_int32_t cpu_counter_last; /* Last compare value loaded */ @@ -536,30 +537,30 @@ * Low level access routines to CPU registers */ -void setsoftintr0(void); -void clearsoftintr0(void); -void setsoftintr1(void); -void clearsoftintr1(void); -void setsr(u_int32_t); +void setsoftintr0(void); +void clearsoftintr0(void); +void setsoftintr1(void); +void clearsoftintr1(void); +void setsr(u_int32_t); u_int32_t getsr(void); u_int32_t mips_cp0_status_read(void); -void mips_cp0_status_write(u_int32_t); +void mips_cp0_status_write(u_int32_t); -int disableintr(void); -void restoreintr(int); -int enableintr(void); -int Mips_TLBGetPID(void); +int disableintr(void); +void restoreintr(int); +int enableintr(void); +int Mips_TLBGetPID(void); -void swi_vm(void *); -void cpu_halt(void); -void cpu_reset(void); +void swi_vm(void *); +void cpu_halt(void); +void cpu_reset(void); u_int32_t set_intr_mask(u_int32_t); u_int32_t get_intr_mask(void); u_int32_t get_cyclecount(void); -#define cpu_spinwait() /* nothing */ +#define cpu_spinwait() /* nothing */ -#endif /* _KERNEL */ -#endif /* !_MACHINE_CPU_H_ */ +#endif /* _KERNEL */ +#endif /* !_MACHINE_CPU_H_ */
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