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Date:      Fri, 1 May 2009 16:10:40 -0400
From:      Jung-uk Kim <jkim@FreeBSD.org>
To:        freebsd-current@FreeBSD.org
Cc:        pluknet <pluknet@gmail.com>, Jeff Roberson <jroberson@jroberson.net>
Subject:   Re: cannot compile sched_ule without options SMP
Message-ID:  <200905011610.42613.jkim@FreeBSD.org>
In-Reply-To: <a31046fc0904302004r195750f2h586e08d9acf854d1@mail.gmail.com>
References:  <20090430013428.cb4f804b.nork@FreeBSD.org> <a31046fc0904301939la407bfek2f342b06c7d3ba29@mail.gmail.com> <a31046fc0904302004r195750f2h586e08d9acf854d1@mail.gmail.com>

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On Thursday 30 April 2009 11:04 pm, pluknet wrote:
> 2009/5/1 pluknet <pluknet@gmail.com>:
> > 2009/5/1 Jeff Roberson <jroberson@jroberson.net>:
> >> On Thu, 30 Apr 2009, pluknet wrote:
> >>> 2009/4/30 Jeff Roberson <jroberson@jroberson.net>:
> >>>> On SMP machines you should now see output like this:
> >>>> FreeBSD/SMP: Multiprocessor System Detected: 8 CPUs
> >>>> FreeBSD/SMP: 1 package(s) x 4 core(s) x 2 SMT threads
> >>>>
> >>>> If you detect any irregularities with kern.sched.topology_spec
> >>>> or this dmesg
> >>>> line please report them.
> >>>
> >>> Hi, Jeff.
> >>>
> >>> I have such mismatch. This is an Intel E7200.
> >>>
> >>> FreeBSD/SMP: Multiprocessor System Detected: 2 CPUs
> >>> FreeBSD/SMP: 1 package(s) x 1 core(s) x 2 HTT threads
> >>> cpu0 (BSP): APIC ID:  0
> >>> cpu1 (AP/HT): APIC ID:  1
> >>>
> >>> So it should be instead: 1 package(s) x 2 core(s)
> >>> cpu0 (BSP): APIC ID:  0
> >>> cpu1 (AP): APIC ID:  1
> >>
> >> Can you please repeat the following steps as I have done here:
> >
> > (kgdb) p/x cpu_high
> > $1 = 0x2
> > (kgdb) p/x cpu_cores
> > $2 = 0x1
> > (kgdb) p/x cpu_logical
> > $3 = 0x2
> > (kgdb) p/x cpu_feature
> > $4 = 0xbfebfbff
> > (kgdb) p/x logical_cpus
> > $5 = 0x2
> > (kgdb) p/x hyperthreading_cpus
> > $6 = 0x2
>
> Follow up myself:
>
> What is embarrassing me is HTT feature enabled. May the reason be
> in a buggy CPUID ?

No, the flag does not mean it supports Hyperthreading.  It means more 
than one logical core is supported (multi-threading) although the 
name didn't change for historical reason. ;-)

Can you try the attached patch?

Thanks!

Jung-uk Kim

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--- sys/amd64/amd64/identcpu.c	29 Apr 2009 06:54:40 -0000	1.172
+++ sys/amd64/amd64/identcpu.c	1 May 2009 20:00:59 -0000
@@ -472,6 +472,24 @@
 	cpu_feature = regs[3];
 	cpu_feature2 = regs[2];
 
+	/*
+	 * Clear "Limit CPUID Maxval" bit and get the highest
+	 * basic CPUID function again if it is set from BIOS.
+	 * It is necessary for probing correct CPU topology later.
+	 * XXX This is only done on BSP.
+	 */
+	if (cpu_vendor_id == CPU_VENDOR_INTEL &&
+	    cpu_high > 0 && cpu_high < 4 &&
+	    (cpu_feature & CPUID_HTT) != 0) {
+		uint64_t msr;
+		msr = rdmsr(MSR_IA32_MISC_ENABLE);
+		if ((msr & 0x400000ULL) != 0) {
+			wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL);
+			do_cpuid(0, regs);
+			cpu_high = regs[0];
+		}
+	}
+
 	if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 	    cpu_vendor_id == CPU_VENDOR_AMD ||
 	    cpu_vendor_id == CPU_VENDOR_CENTAUR) {
--- sys/i386/i386/identcpu.c	29 Apr 2009 06:54:40 -0000	1.201
+++ sys/i386/i386/identcpu.c	1 May 2009 20:00:59 -0000
@@ -323,15 +323,6 @@
 				strcat(cpu_model, "Pentium 4");
 				cpu = CPU_P4;
 				model = (cpu_id & 0x0f0) >> 4;
-				if (model == 3 || model == 4 || model == 6) {
-					uint64_t tmp;
-
-					tmp = rdmsr(MSR_IA32_MISC_ENABLE);
-					wrmsr(MSR_IA32_MISC_ENABLE,
-					      tmp & ~(1LL << 22));
-					do_cpuid(0, regs);
-					cpu_high = regs[0];
-				}
 				break;
 			default:
 				strcat(cpu_model, "unknown");
@@ -1110,6 +1101,24 @@
 
 	cpu_vendor_id = find_cpu_vendor_id();
 
+	/*
+	 * Clear "Limit CPUID Maxval" bit and get the highest
+	 * basic CPUID function again if it is set from BIOS.
+	 * It is necessary for probing correct CPU topology later.
+	 * XXX This is only done on BSP.
+	 */
+	if (cpu_vendor_id == CPU_VENDOR_INTEL &&
+	    cpu_high > 0 && cpu_high < 4 &&
+	    (cpu_feature & CPUID_HTT) != 0) {
+		uint64_t msr;
+		msr = rdmsr(MSR_IA32_MISC_ENABLE);
+		if ((msr & 0x400000ULL) != 0) {
+			wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL);
+			do_cpuid(0, regs);
+			cpu_high = regs[0];
+		}
+	}
+
 	/* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */
 	if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 	    cpu_vendor_id == CPU_VENDOR_AMD) {

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