Date: Sun, 25 Aug 2019 17:28:44 +1000 From: Peter Jeremy <peter@rulingia.com> To: Michal Meloun <mmel@FreeBSD.org> Cc: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: Re: svn commit: r351187 - head/sys/arm64/rockchip Message-ID: <20190825072844.GA4799@server.rulingia.com> In-Reply-To: <201908180919.x7I9JXGj021325@repo.freebsd.org> References: <201908180919.x7I9JXGj021325@repo.freebsd.org>
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On 2019-Aug-18 09:19:33 +0000, Michal Meloun <mmel@FreeBSD.org> wrote:
> Improve rk_pinctrl driver:
Sorry for the late notice but this breaks my Rock64 (RK3328).
I'm using:
U-Boot 2017.09-rockchip-ayufan-1035-gd646df03ac (Oct 26 2018 - 08:36:01 +00=
00)
At r351452, the kernel boot looks like:
=2E..
gic0: <ARM Generic Interrupt Controller> mem 0xff811000-0xff811fff,0xff8120=
00-0xff813fff,0xff814000-0xff815fff,0xff816000-0xff817fff irq 48 on ofwbus0
gic0: pn 0x2, arch 0x2, rev 0x1, implementer 0x43b irqs 160
rk_pinctrl0: <RockChip Pinctrl controller> on ofwbus0
rk_pinctrl0: Cannot attach GPIO subdevice: gpio0@ff210000
rk_pinctrl0: Cannot attach GPIO subdevice: gpio1@ff220000
rk_pinctrl0: Cannot attach GPIO subdevice: gpio2@ff230000
rk_pinctrl0: Cannot attach GPIO subdevice: gpio3@ff240000
panic: acquiring blockable sleep lock with spinlock or critical section hel=
d (sleep mutex) pmap @ /usr/src/sys/arm64/arm64/pmap.c:5819
cpuid =3D 0
time =3D 1
KDB: stack backtrace:
db_trace_self() at db_trace_self_wrapper+0x28
pc =3D 0xffff00000054c9ac lr =3D 0xffff0000000e2908
sp =3D 0xffff000000010100 fp =3D 0xffff000000010310
db_trace_self_wrapper() at vpanic+0x18c
pc =3D 0xffff0000000e2908 lr =3D 0xffff00000027e848
sp =3D 0xffff000000010320 fp =3D 0xffff0000000103c0
vpanic() at panic+0x44
pc =3D 0xffff00000027e848 lr =3D 0xffff00000027e5f8
sp =3D 0xffff0000000103d0 fp =3D 0xffff000000010450
panic() at witness_checkorder+0xa80
pc =3D 0xffff00000027e5f8 lr =3D 0xffff0000002e5348
sp =3D 0xffff000000010460 fp =3D 0xffff0000000104d0
witness_checkorder() at __mtx_lock_flags+0xb0
pc =3D 0xffff0000002e5348 lr =3D 0xffff00000025e574
sp =3D 0xffff0000000104e0 fp =3D 0xffff000000010520
__mtx_lock_flags() at pmap_fault+0x1bc
pc =3D 0xffff00000025e574 lr =3D 0xffff000000566c00
sp =3D 0xffff000000010530 fp =3D 0xffff000000010550
pmap_fault() at data_abort+0xc0
pc =3D 0xffff000000566c00 lr =3D 0xffff000000568a68
sp =3D 0xffff000000010560 fp =3D 0xffff000000010610
data_abort() at do_el1h_sync+0x128
pc =3D 0xffff000000568a68 lr =3D 0xffff0000005688a4
sp =3D 0xffff000000010620 fp =3D 0xffff000000010650
do_el1h_sync() at handle_el1h_sync+0x74
pc =3D 0xffff0000005688a4 lr =3D 0xffff00000054f074
sp =3D 0xffff000000010660 fp =3D 0xffff000000010770
handle_el1h_sync() at simple_mfd_syscon_modify_4+0x60
pc =3D 0xffff00000054f074 lr =3D 0xffff0000000fd334
sp =3D 0xffff000000010780 fp =3D 0xffff000000010830
simple_mfd_syscon_modify_4() at rk_pinctrl_configure_pins+0x1b4
pc =3D 0xffff0000000fd334 lr =3D 0xffff0000005795fc
sp =3D 0xffff000000010840 fp =3D 0xffff0000000108c0
rk_pinctrl_configure_pins() at pinctrl_configure_children+0x120
pc =3D 0xffff0000005795fc lr =3D 0xffff0000000fc4dc
sp =3D 0xffff0000000108d0 fp =3D 0xffff000000010950
pinctrl_configure_children() at fdt_pinctrl_configure_tree+0x20
pc =3D 0xffff0000000fc4dc lr =3D 0xffff0000000fc3a8
sp =3D 0xffff000000010960 fp =3D 0xffff000000010970
fdt_pinctrl_configure_tree() at rk_pinctrl_attach+0x310
pc =3D 0xffff0000000fc3a8 lr =3D 0xffff000000579414
sp =3D 0xffff000000010980 fp =3D 0xffff0000000109e0
rk_pinctrl_attach() at device_attach+0x3f4
pc =3D 0xffff000000579414 lr =3D 0xffff0000002b3f18
sp =3D 0xffff0000000109f0 fp =3D 0xffff000000010a40
device_attach() at bus_generic_new_pass+0x12c
pc =3D 0xffff0000002b3f18 lr =3D 0xffff0000002b5ccc
sp =3D 0xffff000000010a50 fp =3D 0xffff000000010a80
bus_generic_new_pass() at bus_generic_new_pass+0xe4
pc =3D 0xffff0000002b5ccc lr =3D 0xffff0000002b5c84
sp =3D 0xffff000000010a90 fp =3D 0xffff000000010ac0
bus_generic_new_pass() at bus_generic_new_pass+0xe4
pc =3D 0xffff0000002b5c84 lr =3D 0xffff0000002b5c84
sp =3D 0xffff000000010ad0 fp =3D 0xffff000000010b00
bus_generic_new_pass() at bus_set_pass+0x8c
pc =3D 0xffff0000002b5c84 lr =3D 0xffff0000002b1674
sp =3D 0xffff000000010b10 fp =3D 0xffff000000010b40
bus_set_pass() at mi_startup+0x238
pc =3D 0xffff0000002b1674 lr =3D 0xffff000000217b50
sp =3D 0xffff000000010b50 fp =3D 0xffff000000010bb0
mi_startup() at virtdone+0x54
pc =3D 0xffff000000217b50 lr =3D 0xffff000000001084
sp =3D 0xffff000000010bc0 fp =3D 0x0000000000000000
----
When I revert r351187, I get:
=2E..
gic0: <ARM Generic Interrupt Controller> mem 0xff811000-0xff811fff,0xff8120=
00-0xff813fff,0xff814000-0xff815fff,0xff816000-0xff817fff irq 48 on ofwbus0
gic0: pn 0x2, arch 0x2, rev 0x1, implementer 0x43b irqs 160
rk_pinctrl0: <RockChip Pinctrl controller> on ofwbus0
rk_i2c0: <RockChip I2C> mem 0xff160000-0xff160fff irq 16 on ofwbus0
iicbus0: <OFW I2C bus> on rk_i2c0
gpio0: <RockChip GPIO Bank controller> mem 0xff210000-0xff2100ff irq 51 on =
rk_pinctrl0
gpiobus0: <GPIO bus> on gpio0
gpio1: <RockChip GPIO Bank controller> mem 0xff220000-0xff2200ff irq 52 on =
rk_pinctrl0
gpiobus1: <GPIO bus> on gpio1
gpio2: <RockChip GPIO Bank controller> mem 0xff230000-0xff2300ff irq 53 on =
rk_pinctrl0
gpiobus2: <GPIO bus> on gpio2
gpio3: <RockChip GPIO Bank controller> mem 0xff240000-0xff2400ff irq 54 on =
rk_pinctrl0
gpiobus3: <GPIO bus> on gpio3
rk805_pmu0: <RockChip RK805 PMIC> at addr 0x30 irq 55 on iicbus0
=2E..
I haven't dug into this further yet.
--=20
Peter Jeremy
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