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Date:      Sat, 1 May 2010 16:36:15 +0000 (UTC)
From:      Warner Losh <imp@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r207472 - in head/sys: conf dev/ath/ath_hal/ar5212
Message-ID:  <201005011636.o41GaFsK084343@svn.freebsd.org>

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Author: imp
Date: Sat May  1 16:36:14 2010
New Revision: 207472
URL: http://svn.freebsd.org/changeset/base/207472

Log:
  The Atheros AR71xx CPUs, when paired with the AR5212 parts, has a bug
  that generates a fatal bus trap.  Normally, the chips are setup to do
  128 byte DMA bursts, but when on this CPU, they can only safely due
  4-byte DMA bursts due to this bug.  Details of the exact nature of the
  bug are sketchy, but some can be found at
  https://forum.openwrt.org/viewtopic.php?pid=70060 on pages 4, 5 and 6.
  There's a small performance penalty associated with this workaround,
  so it is only enabled when needed on the Atheros AR71xx platforms.
  
  Unfortunately, this condition is impossible to detect at runtime
  without MIPS specific ifdefs.  Rather than cast an overly-broad net
  like Linux/OpenWRT dues (which enables this workaround all the time on
  MIPS32 platforms), we put this option in the kernel for just the
  affected machines.  Sam didn't like this aspect of the patch when he
  reviewed it, and I'd love to hear sane proposals on how to fix it :)
  
  Reviewed by:	sam@

Modified:
  head/sys/conf/NOTES
  head/sys/conf/options
  head/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c

Modified: head/sys/conf/NOTES
==============================================================================
--- head/sys/conf/NOTES	Sat May  1 15:00:00 2010	(r207471)
+++ head/sys/conf/NOTES	Sat May  1 16:36:14 2010	(r207472)
@@ -2091,6 +2091,15 @@ device		ath_hal		# pci/cardbus chip supp
 #device		ath_rf5413
 #device		ath_ar5416	# AR5416 chips
 options 	AH_SUPPORT_AR5416	# enable AR5416 tx/rx descriptors
+# All of the AR5212 parts have a problem when paired with the AR71xx
+# CPUS.  These parts have a bug that triggers a fatal bus error on the AR71xx
+# only.  Details of the exact nature of the bug are sketchy, but some can be
+# found at https://forum.openwrt.org/viewtopic.php?pid=70060 on pages 4, 5 and
+# 6.  This option enables this workaround.  There is a performance penalty
+# for this work around, but without it things don't work at all.  The DMA
+# from the card usually bursts 128 bytes, but on the affected CPUs, only
+# 4 are safe.
+options	   	AH_RXCFG_SDMAMW_4BYTES
 #device		ath_ar9160	# AR9160 chips
 #device		ath_ar9280	# AR9280 chips
 #device		ath_ar9285	# AR9285 chips

Modified: head/sys/conf/options
==============================================================================
--- head/sys/conf/options	Sat May  1 15:00:00 2010	(r207471)
+++ head/sys/conf/options	Sat May  1 16:36:14 2010	(r207472)
@@ -771,6 +771,7 @@ AH_PRIVATE_DIAG		opt_ah.h
 AH_NEED_DESC_SWAP	opt_ah.h
 AH_USE_INIPDGAIN	opt_ah.h
 AH_MAXCHAN		opt_ah.h
+AH_RXCFG_SDMAMW_4BYTES	opt_ah.h
 
 # options for the Broadcom BCM43xx driver (bwi)
 BWI_DEBUG		opt_bwi.h

Modified: head/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c
==============================================================================
--- head/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c	Sat May  1 15:00:00 2010	(r207471)
+++ head/sys/dev/ath/ath_hal/ar5212/ar5212_reset.c	Sat May  1 16:36:14 2010	(r207472)
@@ -283,6 +283,14 @@ ar5212Reset(struct ath_hal *ah, HAL_OPMO
 	regWrites = ath_hal_ini_write(ah, &ahp->ah_ini_modes, modesIndex, 0);
 	regWrites = write_common(ah, &ahp->ah_ini_common, bChannelChange,
 		regWrites);
+#ifdef AH_RXCFG_SDMAMW_4BYTES
+	/*
+	 * Nala doesn't work with 128 byte bursts on pb42(hydra) (ar71xx),
+	 * use 4 instead.  Enabling it on all platforms would hurt performance,
+	 * so we only enable it on the ones that are affected by it.
+	 */
+	OS_REG_WRITE(ah, AR_RXCFG, 0);
+#endif
 	ahp->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites);
 
 	OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);



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