Date: Sat, 23 Aug 2014 17:19:21 +0000 (UTC) From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@freebsd.org, svn-src-projects@freebsd.org Subject: svn commit: r270422 - projects/arm64/sys/arm64/arm64 Message-ID: <201408231719.s7NHJLNU032338@svn.freebsd.org>
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Author: andrew Date: Sat Aug 23 17:19:21 2014 New Revision: 270422 URL: http://svnweb.freebsd.org/changeset/base/270422 Log: Handle more exceptions. While here clean up the vector macros to only use one as they were identical other than the location to branch to. Modified: projects/arm64/sys/arm64/arm64/exception.S projects/arm64/sys/arm64/arm64/trap.c Modified: projects/arm64/sys/arm64/arm64/exception.S ============================================================================== --- projects/arm64/sys/arm64/arm64/exception.S Sat Aug 23 17:19:18 2014 (r270421) +++ projects/arm64/sys/arm64/arm64/exception.S Sat Aug 23 17:19:21 2014 (r270422) @@ -110,48 +110,61 @@ handle_el1h_irq: restore_registers eret -.macro vempty - .align 7 - EMIT('Z'); - 1: b 1b -.endm +handle_el1h_error: + brk 0xf13 -.macro el1h_sync - .align 7 - b handle_el1h_sync -.endm +handle_el0_sync: + save_registers + mov x0, sp + bl do_el0_sync + restore_registers + eret -.macro el1h_irq +handle_el0_irq: + save_registers + mov x0, sp + bl cpu_intr + restore_registers + eret + +handle_el0_error: + save_registers + mov x0, sp + bl do_el0_error + brk 0xf23 + 1: b 1b + +.macro vempty .align 7 - b handle_el1h_irq + brk 0xfff + 1: b 1b .endm -.macro el1h_error +.macro vector name .align 7 - EMIT('C'); - 1: b 1b + b handle_\name .endm .align 11 .globl exception_vectors exception_vectors: - vempty /* Synchronous EL1t */ - vempty /* IRQ EL1t */ - vempty /* FIQ EL1t */ - vempty /* Error EL1t */ - - el1h_sync /* Synchronous EL1h */ - el1h_irq /* IRQ EL1h */ - vempty /* FIQ EL1h */ - el1h_error /* Error EL1h */ - - vempty /* Synchronous 64-bit EL0 */ - vempty /* IRQ 64-bit EL0 */ - vempty /* FIQ 64-bit EL0 */ - vempty /* Error 64-bit EL0 */ - - vempty /* Synchronous 32-bit EL0 */ - vempty /* IRQ 32-bit EL0 */ - vempty /* FIQ 32-bit EL0 */ - vempty /* Error 32-bit EL0 */ + vempty /* Synchronous EL1t */ + vempty /* IRQ EL1t */ + vempty /* FIQ EL1t */ + vempty /* Error EL1t */ + + vector el1h_sync /* Synchronous EL1h */ + vector el1h_irq /* IRQ EL1h */ + vempty /* FIQ EL1h */ + vector el1h_error /* Error EL1h */ + + vector el0_sync /* Synchronous 64-bit EL0 */ + vector el0_irq /* IRQ 64-bit EL0 */ + vempty /* FIQ 64-bit EL0 */ + vector el0_error /* Error 64-bit EL0 */ + + vempty /* Synchronous 32-bit EL0 */ + vempty /* IRQ 32-bit EL0 */ + vempty /* FIQ 32-bit EL0 */ + vempty /* Error 32-bit EL0 */ Modified: projects/arm64/sys/arm64/arm64/trap.c ============================================================================== --- projects/arm64/sys/arm64/arm64/trap.c Sat Aug 23 17:19:18 2014 (r270421) +++ projects/arm64/sys/arm64/arm64/trap.c Sat Aug 23 17:19:21 2014 (r270422) @@ -44,6 +44,8 @@ __FBSDID("$FreeBSD$"); /* Called from exception.S */ void do_el1h_sync(struct trapframe *); +void do_el0_sync(struct trapframe *); +void do_el0_error(struct trapframe *); int cpu_fetch_syscall_args(struct thread *td, struct syscall_args *sa) @@ -145,3 +147,47 @@ do_el1h_sync(struct trapframe *frame) printf("Done do_el1h_sync\n"); } +void +do_el0_sync(struct trapframe *frame) +{ + uint32_t exception; + uint64_t esr; + u_int reg; + + __asm __volatile("mrs %x0, esr_el1" : "=&r"(esr)); + exception = (esr >> 26) & 0x3f; + printf("In do_el0_sync %llx %llx %x\n", frame->tf_elr, esr, exception); + + for (reg = 0; reg < 31; reg++) { + printf(" %sx%d: %llx\n", (reg < 10) ? " " : "", reg, frame->tf_x[reg]); + } + printf(" sp: %llx\n", frame->tf_sp); + printf(" lr: %llx\n", frame->tf_lr); + printf(" elr: %llx\n", frame->tf_elr); + printf("spsr: %llx\n", frame->tf_spsr); + + switch(exception) { + case 0x20: + case 0x24: + data_abort(frame, esr, 1); + break; + default: + panic("Unknown exception %x\n", exception); + } +} + +void +do_el0_error(struct trapframe *frame) +{ + u_int reg; + + for (reg = 0; reg < 31; reg++) { + printf(" %sx%d: %llx\n", (reg < 10) ? " " : "", reg, frame->tf_x[reg]); + } + printf(" sp: %llx\n", frame->tf_sp); + printf(" lr: %llx\n", frame->tf_lr); + printf(" elr: %llx\n", frame->tf_elr); + printf("spsr: %llx\n", frame->tf_spsr); + panic("do_el0_error"); +} +
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