Date: Sat, 12 Nov 2016 23:15:52 -0800 From: Adrian Chadd <adrian.chadd@gmail.com> To: Warner Losh <imp@bsdimp.com> Cc: Konstantin Belousov <kostikbel@gmail.com>, "svn-src-head@freebsd.org" <svn-src-head@freebsd.org>, "svn-src-all@freebsd.org" <svn-src-all@freebsd.org>, "src-committers@freebsd.org" <src-committers@freebsd.org>, "freebsd-mips@freebsd.org" <freebsd-mips@freebsd.org> Subject: Re: svn commit: r307626 - head/sys/ufs/ffs Message-ID: <CAJ-VmomOpX6_6EKjmqNM09mscqNGiNRBVMDiPCtsjPRsAHiWZQ@mail.gmail.com> In-Reply-To: <CANCZdfreg9wD-2pdGtzgeO86BptSE4M7LnLFTC09K3RHyHR8cQ@mail.gmail.com> References: <201610191109.u9JB9TTC002727@repo.freebsd.org> <CAJ-Vmom5rYe89m7bch4qoHHq3X2e67pPk_7G2aRGrjSPNp5mzg@mail.gmail.com> <20161113065851.GD54029@kib.kiev.ua> <CANCZdfreg9wD-2pdGtzgeO86BptSE4M7LnLFTC09K3RHyHR8cQ@mail.gmail.com>
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On 12 November 2016 at 23:12, Warner Losh <imp@bsdimp.com> wrote: > On Sat, Nov 12, 2016 at 11:58 PM, Konstantin Belousov > <kostikbel@gmail.com> wrote: >> On Sat, Nov 12, 2016 at 03:19:13PM -0800, Adrian Chadd wrote: >>> hi! >>> >>> This broke freebsd on mips24k. >>> >>> BAD_PAGE_FAULT: pid 1 tid 100001 (init), uid 0: pc 0x4002a4 got a read >>> fault (type 0x2) at 0 >>> Trapframe Register Dump: >>> zero: 0 at: 0 v0: 0 v1: 0 >>> a0: 0x7fffeecc a1: 0 a2: 0 a3: 0 >>> t0: 0 t1: 0 t2: 0 t3: 0 >>> t4: 0 t5: 0 t6: 0 t7: 0 >>> t8: 0 t9: 0x400260 s0: 0x10 s1: 0x2 >>> s2: 0x7fffeed0 s3: 0 s4: 0 s5: 0 >>> s6: 0 s7: 0 k0: 0 k1: 0 >>> gp: 0x4d55d0 sp: 0x7ffeee90 s8: 0 ra: 0 >>> sr: 0xfc13 mullo: 0 mulhi: 0 badvaddr: 0 >>> cause: 0x8 pc: 0x4002a4 >>> Page table info for pc address 0x4002a4: pde = 0x809be000, pte = 0xa001acda >>> Dumping 4 words starting at pc address 0x4002a4: >>> 8c420000 14400003 00908021 8f828024 >>> Page table info for bad address 0: pde = 0, pte = 0 >> MIPS24k has split I/D caches, and both are VIPT, am I right ? >> I was not able to find the handling of cache aliasing in mips/pmap.c. >> >> Still, I am curious whether setting the loader tunable vfs.buf_pager_relbuf >> to 1 change anything. > > MIPS caches are such that creating two virtual mappings to the same > physical page will cause corruption. It's simply not allowed, at least > for the class of MIPS machines I used to bring up the port originally. Hi, Right - the bulk of MIPS hardware (including 24k/74k) are VIPT, and we're not allowed to do cache aliasing in that manner. -adrian
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