Date: Mon, 11 May 2020 18:47:52 +0000 (UTC) From: John Baldwin <jhb@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r360904 - stable/12/sys/riscv/include Message-ID: <202005111847.04BIlqrO038407@repo.freebsd.org>
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Author: jhb Date: Mon May 11 18:47:51 2020 New Revision: 360904 URL: https://svnweb.freebsd.org/changeset/base/360904 Log: MFC 357595: Fix EXCP_MASK to include all relevant bits from scause. While cause codes higher than 16 are reserved, the exception code field of the register is defined to be all bits but the upper-most bit. Modified: stable/12/sys/riscv/include/riscvreg.h Directory Properties: stable/12/ (props changed) Modified: stable/12/sys/riscv/include/riscvreg.h ============================================================================== --- stable/12/sys/riscv/include/riscvreg.h Mon May 11 18:47:38 2020 (r360903) +++ stable/12/sys/riscv/include/riscvreg.h Mon May 11 18:47:51 2020 (r360904) @@ -37,8 +37,7 @@ #ifndef _MACHINE_RISCVREG_H_ #define _MACHINE_RISCVREG_H_ -#define EXCP_SHIFT 0 -#define EXCP_MASK (0xf << EXCP_SHIFT) +#define EXCP_MASK (~EXCP_INTR) #define EXCP_MISALIGNED_FETCH 0 #define EXCP_FAULT_FETCH 1 #define EXCP_ILLEGAL_INSTRUCTION 2
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