Date: Mon, 4 Jul 2022 16:40:12 GMT From: Mitchell Horne <mhorne@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org Subject: git: f0577f42b24a - stable/13 - riscv timer: remove intermediate helper Message-ID: <202207041640.264GeCMx045118@gitrepo.freebsd.org>
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The branch stable/13 has been updated by mhorne: URL: https://cgit.FreeBSD.org/src/commit/?id=f0577f42b24a699f56c910e54551e9e7f8e7c9d3 commit f0577f42b24a699f56c910e54551e9e7f8e7c9d3 Author: Mitchell Horne <mhorne@FreeBSD.org> AuthorDate: 2022-06-21 16:23:21 +0000 Commit: Mitchell Horne <mhorne@FreeBSD.org> CommitDate: 2022-07-04 16:37:05 +0000 riscv timer: remove intermediate helper get_counts() doesn't do anything at the moment but return the result of get_cycles(), so remove it. For clarity, rename get_cycles() to get_timecount(); RISC-V defines separate time and cyclecount CSRs, so let's avoid confusing the two. They may be backed by the same underlying clock, but this is an implementation detail. MFC after: 1 week Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D35461 (cherry picked from commit b82f4170fca86e9b41b613715852d4f225b26e3a) --- sys/riscv/riscv/timer.c | 25 ++++++------------------- 1 file changed, 6 insertions(+), 19 deletions(-) diff --git a/sys/riscv/riscv/timer.c b/sys/riscv/riscv/timer.c index c852d3dbe0f1..9c333b42059e 100644 --- a/sys/riscv/riscv/timer.c +++ b/sys/riscv/riscv/timer.c @@ -78,30 +78,17 @@ static struct timecounter riscv_timer_timecount = { }; static inline uint64_t -get_cycles(void) +get_timecount(void) { return (rdtime()); } -static long -get_counts(struct riscv_timer_softc *sc) -{ - uint64_t counts; - - counts = get_cycles(); - - return (counts); -} - static u_int -riscv_timer_tc_get_timecount(struct timecounter *tc) +riscv_timer_tc_get_timecount(struct timecounter *tc __unused) { - struct riscv_timer_softc *sc; - - sc = tc->tc_priv; - return (get_counts(sc)); + return (get_timecount()); } static uint32_t @@ -120,7 +107,7 @@ riscv_timer_et_start(struct eventtimer *et, sbintime_t first, sbintime_t period) if (first != 0) { counts = ((uint32_t)et->et_frequency * first) >> 32; - sbi_set_timer(get_cycles() + counts); + sbi_set_timer(get_timecount() + counts); csr_set(sie, SIE_STIE); return (0); @@ -291,10 +278,10 @@ DELAY(int usec) else counts = usec * counts_per_usec; - first = get_counts(riscv_timer_sc); + first = get_timecount(); while (counts > 0) { - last = get_counts(riscv_timer_sc); + last = get_timecount(); counts -= (int64_t)(last - first); first = last; }
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