Date: Fri, 28 Dec 2018 08:47:53 +0000 (UTC) From: Andriy Gapon <avg@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r342564 - stable/12/sys/dev/ichwd Message-ID: <201812280847.wBS8lrCI006756@repo.freebsd.org>
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Author: avg Date: Fri Dec 28 08:47:52 2018 New Revision: 342564 URL: https://svnweb.freebsd.org/changeset/base/342564 Log: MFC r342072: ichwd: add support for clearing No Reboot bit in TCOv4 Modified: stable/12/sys/dev/ichwd/ichwd.c stable/12/sys/dev/ichwd/ichwd.h Directory Properties: stable/12/ (props changed) Modified: stable/12/sys/dev/ichwd/ichwd.c ============================================================================== --- stable/12/sys/dev/ichwd/ichwd.c Fri Dec 28 01:34:08 2018 (r342563) +++ stable/12/sys/dev/ichwd/ichwd.c Fri Dec 28 08:47:52 2018 (r342564) @@ -76,6 +76,10 @@ __FBSDID("$FreeBSD$"); #include <dev/ichwd/ichwd.h> +#include <x86/pci_cfgreg.h> +#include <dev/pci/pcivar.h> +#include <dev/pci/pci_private.h> + static struct ichwd_device ichwd_devices[] = { { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1, 1 }, { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1, 1 }, @@ -309,6 +313,8 @@ static devclass_t ichwd_devclass; /* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */ #define ichwd_read_pmc_4(sc, off) \ bus_read_4((sc)->gcs_res, (off)) +#define ichwd_read_gc_4(sc, off) \ + bus_read_4((sc)->gc_res, (off)) #define ichwd_write_tco_1(sc, off, val) \ bus_write_1((sc)->tco_res, (off), (val)) @@ -323,6 +329,8 @@ static devclass_t ichwd_devclass; /* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */ #define ichwd_write_pmc_4(sc, off, val) \ bus_write_4((sc)->gcs_res, (off), (val)) +#define ichwd_write_gc_4(sc, off, val) \ + bus_write_4((sc)->gc_res, (off), (val)) #define ichwd_verbose_printf(dev, ...) \ do { \ @@ -495,9 +503,12 @@ ichwd_clear_noreboot(struct ichwd_softc *sc) rc = EIO; break; case 4: - /* - * TODO. This needs access to a hidden PCI device at 31:1. - */ + status = ichwd_read_gc_4(sc, 0); + status &= ~SMB_GC_NO_REBOOT; + ichwd_write_gc_4(sc, 0, status); + status = ichwd_read_gc_4(sc, 0); + if (status & SMB_GC_NO_REBOOT) + rc = EIO; break; default: ichwd_verbose_printf(sc->device, @@ -611,6 +622,7 @@ ichwd_identify(driver_t *driver, device_t parent) struct ichwd_device *id_p; device_t ich, smb; device_t dev; + uint64_t base_address64; uint32_t base_address; uint32_t ctl; int rc; @@ -671,6 +683,33 @@ ichwd_identify(driver_t *driver, device_t parent) "Can not set TCO v%d I/O resource (err = %d)\n", id_p->tco_version, rc); } + + /* + * Unhide Primary to Sideband Bridge (P2SB) PCI device, so that + * we can discover the base address of Private Configuration + * Space via the bridge's BAR. + * Then hide back the bridge. + */ + pci_cfgregwrite(0, 31, 1, 0xe1, 0, 1); + base_address64 = pci_cfgregread(0, 31, 1, SBREG_BAR + 4, 4); + base_address64 <<= 32; + base_address64 |= pci_cfgregread(0, 31, 1, SBREG_BAR, 4); + base_address64 &= ~0xfull; + pci_cfgregwrite(0, 31, 1, 0xe1, 1, 1); + + /* + * No Reboot bit is in General Control register, offset 0xc, + * within the SMBus target port, ID 0xc6. + */ + base_address64 += PCR_REG_OFF(SMB_PORT_ID, SMB_GC_REG); + rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, base_address64, + SMB_GC_SIZE); + if (rc != 0) { + ichwd_verbose_printf(dev, + "Can not set TCO v%d PCR I/O resource (err = %d)\n", + id_p->tco_version, rc); + } + break; default: ichwd_verbose_printf(dev, @@ -723,6 +762,18 @@ ichwd_smb_attach(device_t dev) return (ENXIO); } + /* + * Allocate General Control I/O register in PCH + * Private Configuration Space (PCR). + */ + sc->gc_rid = 1; + sc->gc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->gc_rid, + RF_ACTIVE | RF_SHAREABLE); + if (sc->gc_res == NULL) { + device_printf(dev, "unable to reserve hidden P2SB registers\n"); + return (ENXIO); + } + /* Get ACPI base address. */ isab = device_get_parent(device_get_parent(dev)); pmdev = pci_find_dbsf(pci_get_domain(isab), pci_get_bus(isab), 31, 2); @@ -737,7 +788,7 @@ ichwd_smb_attach(device_t dev) } /* Allocate SMI control I/O register space. */ - sc->smi_rid = 1; + sc->smi_rid = 2; sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, acpi_base + SMI_BASE, acpi_base + SMI_BASE + SMI_LEN - 1, SMI_LEN, RF_ACTIVE | RF_SHAREABLE); @@ -854,6 +905,9 @@ ichwd_attach(device_t dev) if (sc->gcs_res != NULL) bus_release_resource(sc->ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res); + if (sc->gc_res != NULL) + bus_release_resource(dev, SYS_RES_MEMORY, + sc->gc_rid, sc->gc_res); return (ENXIO); } @@ -889,6 +943,9 @@ ichwd_detach(device_t dev) if (sc->gcs_res) bus_release_resource(sc->ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res); + if (sc->gc_res) + bus_release_resource(dev, SYS_RES_MEMORY, sc->gc_rid, + sc->gc_res); return (0); } Modified: stable/12/sys/dev/ichwd/ichwd.h ============================================================================== --- stable/12/sys/dev/ichwd/ichwd.h Fri Dec 28 01:34:08 2018 (r342563) +++ stable/12/sys/dev/ichwd/ichwd.h Fri Dec 28 08:47:52 2018 (r342564) @@ -59,6 +59,9 @@ struct ichwd_softc { int gcs_rid; struct resource *gcs_res; + int gc_rid; + struct resource *gc_res; + eventhandler_tag ev_tag; }; @@ -299,6 +302,18 @@ struct ichwd_softc { #define ICH_TCOCTL 0x54 /* TCO Control */ #define ICH_TCOCTL_TCO_BASE_EN 0x0100 /* TCO Base decoding enabled */ #define ICH_TCOCTL_TCO_BASE_LOCK 0x0001 /* TCOBASE is locked */ + +/* + * Configuration registers in Sunrise Point and Lewisburg PCH Sideband Interface + * and Private Configuration Space. + */ +#define SBREG_BAR 0x10 +#define SMB_GC_REG 0xc +#define SMB_GC_SIZE 4 +#define SMB_GC_NO_REBOOT 0x2 +#define SMB_PORT_ID 0xc6 +#define PCR_PORTID_SHIFT 16 +#define PCR_REG_OFF(pid, reg) (((pid) << PCR_PORTID_SHIFT) | (reg)) /* register names and locations (relative to PMBASE) */ #define SMI_BASE 0x30 /* base address for SMI registers */
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