Date: Tue, 20 Mar 2007 14:27:49 -0700 From: John Polstra <jdp@polstra.com> To: Jung-uk Kim <jkim@FreeBSD.org> Cc: cvs-src@FreeBSD.org, src-committers@FreeBSD.org, cvs-all@FreeBSD.org Subject: Re: cvs commit: src/sys/dev/mii brgphy.c Message-ID: <460051D5.80305@polstra.com> In-Reply-To: <200703201648.09419.jkim@FreeBSD.org> References: <200703192317.l2JNHd59062213@repoman.freebsd.org> <460035F8.3080507@polstra.com> <200703201648.09419.jkim@FreeBSD.org>
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Jung-uk Kim wrote: > On Tuesday 20 March 2007 03:28 pm, John Polstra wrote: >> Jung-uk Kim wrote: >>> jkim 2007-03-19 23:17:39 UTC >>> >>> FreeBSD src repository >>> >>> Modified files: >>> sys/dev/mii brgphy.c >>> Log: >>> Revert couple of changes from 1.51 and 1.52. Reading link >>> status with BMSR is okay for most of the chipsets but BCM5701 PHY >>> does not seem to like it. >> I'm not sure what you mean by "does not seem to like it", but did >> you try reading the BMSR twice? The link status bit is a latching >> bit. If you read the register once and it shows no link status, >> that only means that at some point since you previously read the >> register, link was lost. It says nothing about the current status >> of link. The only way to find out the current status of link is to >> read the register twice. The first read clears the latch, and the >> second read reports the current status. This is not specific to >> the Broadcom chips. It is standard across all PHYs. > > Believe me, I know that. ;-) I was experimenting on brgphy.c some > time ago and discovered all of my Broadcom PHYs are not 'standard' > PHYs (in your definition), i.e., BMSR's link status bit is not > latching. The Broadcom docs I have seen document the bit as latching. Of course, the docs aren't necessarily correct. :-) John
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