Date: Thu, 10 Jun 2010 20:26:34 +0000 (UTC) From: Rui Paulo <rpaulo@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-8@freebsd.org Subject: svn commit: r209009 - in stable/8/sys/dev/ath/ath_hal: . ar5416 Message-ID: <201006102026.o5AKQYK5056232@svn.freebsd.org>
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Author: rpaulo Date: Thu Jun 10 20:26:34 2010 New Revision: 209009 URL: http://svn.freebsd.org/changeset/base/209009 Log: MFC r208711: Bring in a couple of fixes from the Linux ath9k related to chip hangs. While there, try to make the register write pattern look like what's done by ath9k. Approved by: re (kensmith) Modified: stable/8/sys/dev/ath/ath_hal/ah.h stable/8/sys/dev/ath/ath_hal/ah_eeprom_v4k.c stable/8/sys/dev/ath/ath_hal/ah_eeprom_v4k.h stable/8/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c stable/8/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c stable/8/sys/dev/ath/ath_hal/ar5416/ar5416phy.h stable/8/sys/dev/ath/ath_hal/ar5416/ar5416reg.h stable/8/sys/dev/ath/ath_hal/ar5416/ar9285_attach.c Directory Properties: stable/8/sys/ (props changed) stable/8/sys/amd64/include/xen/ (props changed) stable/8/sys/cddl/contrib/opensolaris/ (props changed) stable/8/sys/contrib/dev/acpica/ (props changed) stable/8/sys/contrib/pf/ (props changed) stable/8/sys/dev/xen/xenpci/ (props changed) stable/8/sys/geom/sched/ (props changed) Modified: stable/8/sys/dev/ath/ath_hal/ah.h ============================================================================== --- stable/8/sys/dev/ath/ath_hal/ah.h Thu Jun 10 20:23:20 2010 (r209008) +++ stable/8/sys/dev/ath/ath_hal/ah.h Thu Jun 10 20:26:34 2010 (r209009) @@ -324,6 +324,7 @@ typedef enum { HAL_INT_RXORN = 0x00000020, HAL_INT_TX = 0x00000040, /* Non-common mapping */ HAL_INT_TXDESC = 0x00000080, + HAL_INT_TIM_TIMER= 0x00000100, HAL_INT_TXURN = 0x00000800, HAL_INT_MIB = 0x00001000, HAL_INT_RXPHY = 0x00004000, Modified: stable/8/sys/dev/ath/ath_hal/ah_eeprom_v4k.c ============================================================================== --- stable/8/sys/dev/ath/ath_hal/ah_eeprom_v4k.c Thu Jun 10 20:23:20 2010 (r209008) +++ stable/8/sys/dev/ath/ath_hal/ah_eeprom_v4k.c Thu Jun 10 20:26:34 2010 (r209009) @@ -38,11 +38,8 @@ v4kEepromGet(struct ath_hal *ah, int par int i; switch (param) { - case AR_EEP_NFTHRESH_5: - *(int16_t *)val = pModal[0].noiseFloorThreshCh[0]; - return HAL_OK; case AR_EEP_NFTHRESH_2: - *(int16_t *)val = pModal[1].noiseFloorThreshCh[0]; + *(int16_t *)val = pModal->noiseFloorThreshCh[0]; return HAL_OK; case AR_EEP_MACADDR: /* Get MAC Address */ sum = 0; @@ -67,14 +64,10 @@ v4kEepromGet(struct ath_hal *ah, int par return pBase->opCapFlags; case AR_EEP_RFSILENT: return pBase->rfSilent; - case AR_EEP_OB_5: - return pModal[CHAN_A_IDX].ob; - case AR_EEP_DB_5: - return pModal[CHAN_A_IDX].db; case AR_EEP_OB_2: - return pModal[CHAN_B_IDX].ob; + return pModal->ob; case AR_EEP_DB_2: - return pModal[CHAN_B_IDX].db; + return pModal->db; case AR_EEP_TXMASK: return pBase->txMask; case AR_EEP_RXMASK: @@ -84,11 +77,9 @@ v4kEepromGet(struct ath_hal *ah, int par case AR_EEP_TXGAIN_TYPE: return IS_VERS(>=, AR5416_EEP_MINOR_VER_19) ? pBase->txGainType : AR5416_EEP_TXGAIN_ORIG; -#if 0 case AR_EEP_OL_PWRCTRL: HALASSERT(val == AH_NULL); - return pBase->openLoopPwrCntl ? HAL_OK : HAL_EIO; -#endif + return HAL_EIO; case AR_EEP_AMODE: HALASSERT(val == AH_NULL); return pBase->opCapFlags & AR5416_OPFLAGS_11A ? @@ -110,15 +101,11 @@ v4kEepromGet(struct ath_hal *ah, int par case AR_EEP_AES: case AR_EEP_BURST: case AR_EEP_RFKILL: - case AR_EEP_TURBO5DISABLE: case AR_EEP_TURBO2DISABLE: HALASSERT(val == AH_NULL); return HAL_OK; case AR_EEP_ANTGAINMAX_2: - *(int8_t *) val = ee->ee_antennaGainMax[1]; - return HAL_OK; - case AR_EEP_ANTGAINMAX_5: - *(int8_t *) val = ee->ee_antennaGainMax[0]; + *(int8_t *) val = ee->ee_antennaGainMax; return HAL_OK; default: HALASSERT(0); @@ -136,10 +123,7 @@ v4kEepromSet(struct ath_hal *ah, int par switch (param) { case AR_EEP_ANTGAINMAX_2: - ee->ee_antennaGainMax[1] = (int8_t) v; - return HAL_OK; - case AR_EEP_ANTGAINMAX_5: - ee->ee_antennaGainMax[0] = (int8_t) v; + ee->ee_antennaGainMax = (int8_t) v; return HAL_OK; } return HAL_EINVAL; @@ -252,7 +236,7 @@ v4kEepromReadCTLInfo(struct ath_hal *ah, RD_EDGES_POWER *rep = ee->ee_rdEdgesPower; int i, j; - HALASSERT(AR5416_NUM_CTLS <= sizeof(ee->ee_rdEdgesPower)/NUM_EDGES); + HALASSERT(AR5416_4K_NUM_CTLS <= sizeof(ee->ee_rdEdgesPower)/NUM_EDGES); for (i = 0; ee->ee_base.ctlIndex[i] != 0 && i < AR5416_4K_NUM_CTLS; i++) { for (j = 0; j < NUM_EDGES; j ++) { Modified: stable/8/sys/dev/ath/ath_hal/ah_eeprom_v4k.h ============================================================================== --- stable/8/sys/dev/ath/ath_hal/ah_eeprom_v4k.h Thu Jun 10 20:23:20 2010 (r209008) +++ stable/8/sys/dev/ath/ath_hal/ah_eeprom_v4k.h Thu Jun 10 20:26:34 2010 (r209009) @@ -23,6 +23,8 @@ #include "ah_eeprom.h" #include "ah_eeprom_v14.h" +#define AR9285_RDEXT_DEFAULT 0x1F + #undef owl_eep_start_loc #ifdef __LINUX_ARM_ARCH__ /* AP71 */ #define owl_eep_start_loc 0 @@ -150,6 +152,6 @@ typedef struct { uint16_t ee_numCtls; RD_EDGES_POWER ee_rdEdgesPower[NUM_EDGES*AR5416_4K_NUM_CTLS]; /* XXX these are dynamically calculated for use by shared code */ - int8_t ee_antennaGainMax[2]; + int8_t ee_antennaGainMax; } HAL_EEPROM_v4k; #endif /* _AH_EEPROM_V4K_H_ */ Modified: stable/8/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c ============================================================================== --- stable/8/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c Thu Jun 10 20:23:20 2010 (r209008) +++ stable/8/sys/dev/ath/ath_hal/ar5416/ar5416_interrupts.c Thu Jun 10 20:26:34 2010 (r209009) @@ -120,6 +120,13 @@ ar5416GetPendingInterrupts(struct ath_ha ahp->ah_intrTxqs |= MS(isr1, AR_ISR_S1_QCU_TXEOL); } + if (AR_SREV_MERLIN(ah) || AR_SREV_KITE(ah)) { + uint32_t isr5; + isr5 = OS_REG_READ(ah, AR_ISR_S5_S); + if (isr5 & AR_ISR_S5_TIM_TIMER) + *masked |= HAL_INT_TIM_TIMER; + } + /* Interrupt Mitigation on AR5416 */ #ifdef AR5416_INT_MITIGATION if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM)) Modified: stable/8/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c ============================================================================== --- stable/8/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Thu Jun 10 20:23:20 2010 (r209008) +++ stable/8/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Thu Jun 10 20:26:34 2010 (r209009) @@ -170,7 +170,16 @@ ar5416Reset(struct ath_hal *ah, HAL_OPMO OS_REG_WRITE(ah, AR_RSSI_THR, rssiThrReg); OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); + if (AR_SREV_MERLIN_10_OR_LATER(ah)) + OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); + if (AR_SREV_KITE(ah)) { + uint32_t val; + val = OS_REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); + val &= ~AR_PHY_RIFS_INIT_DELAY; + OS_REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val); + } + AH5416(ah)->ah_writeIni(ah, chan); /* Setup 11n MAC/Phy mode registers */ @@ -1019,8 +1028,11 @@ ar5416SetResetPowerOn(struct ath_hal *ah /* * RTC reset and clear */ + OS_REG_WRITE(ah, AR_RC, AR_RC_AHB); OS_REG_WRITE(ah, AR_RTC_RESET, 0); OS_DELAY(20); + OS_REG_WRITE(ah, AR_RC, 0); + OS_REG_WRITE(ah, AR_RTC_RESET, 1); /* Modified: stable/8/sys/dev/ath/ath_hal/ar5416/ar5416phy.h ============================================================================== --- stable/8/sys/dev/ath/ath_hal/ar5416/ar5416phy.h Thu Jun 10 20:23:20 2010 (r209008) +++ stable/8/sys/dev/ath/ath_hal/ar5416/ar5416phy.h Thu Jun 10 20:26:34 2010 (r209009) @@ -111,6 +111,9 @@ #define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0 +#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99ec +#define AR_PHY_RIFS_INIT_DELAY 0x03ff0000 + #define AR_PHY_M_SLEEP 0x99f0 /* sleep control registers */ #define AR_PHY_REFCLKDLY 0x99f4 #define AR_PHY_REFCLKPD 0x99f8 Modified: stable/8/sys/dev/ath/ath_hal/ar5416/ar5416reg.h ============================================================================== --- stable/8/sys/dev/ath/ath_hal/ar5416/ar5416reg.h Thu Jun 10 20:23:20 2010 (r209008) +++ stable/8/sys/dev/ath/ath_hal/ar5416/ar5416reg.h Thu Jun 10 20:26:34 2010 (r209009) @@ -127,6 +127,7 @@ #define AR_EXTRCCNT 0x8328 /* extension channel rx clear count */ #define AR_SELFGEN_MASK 0x832c /* rx and cal chain masks */ #define AR_PCU_TXBUF_CTRL 0x8340 +#define AR_PCU_MISC_MODE2 0x8344 /* DMA & PCI Registers in PCI space (usable during sleep)*/ #define AR_RC_AHB 0x00000001 /* AHB reset */ @@ -244,6 +245,10 @@ #define AR_ISR_S2_GTT 0x00800000 /* Global transmit timeout */ #define AR_ISR_S2_TSFOOR 0x40000000 /* RX TSF out of range */ +#define AR_ISR_S5 0x0098 +#define AR_ISR_S5_S 0x00d8 +#define AR_ISR_S5_TIM_TIMER 0x00000010 + #define AR_INTR_SPURIOUS 0xffffffff #define AR_INTR_RTC_IRQ 0x00000001 /* rtc in shutdown state */ #define AR_INTR_MAC_IRQ 0x00000002 /* pending mac interrupt */ @@ -495,6 +500,8 @@ #define AR_PCU_CLEAR_VMF 0x01000000 /* clear vmf mode (fast cc)*/ #define AR_PCU_CLEAR_BA_VALID 0x04000000 /* clear ba state */ +#define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 + /* GPIO Interrupt */ #define AR_INTR_GPIO 0x3FF00000 /* gpio interrupted */ #define AR_INTR_GPIO_S 20 @@ -521,6 +528,8 @@ #define AR_GPIO_INTR_POL_VAL 0x1FFF #define AR_GPIO_INTR_POL_VAL_S 0 +#define AR_GPIO_JTAG_DISABLE 0x00020000 + #define AR_2040_JOINED_RX_CLEAR 0x00000001 /* use ctl + ext rx_clear for cca */ #define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF Modified: stable/8/sys/dev/ath/ath_hal/ar5416/ar9285_attach.c ============================================================================== --- stable/8/sys/dev/ath/ath_hal/ar5416/ar9285_attach.c Thu Jun 10 20:23:20 2010 (r209008) +++ stable/8/sys/dev/ath/ath_hal/ar5416/ar9285_attach.c Thu Jun 10 20:26:34 2010 (r209009) @@ -316,6 +316,16 @@ ar9285WriteIni(struct ath_hal *ah, const regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 1, regWrites); + OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); + + if (AR_SREV_MERLIN_10_OR_LATER(ah)) { + uint32_t val; + val = OS_REG_READ(ah, AR_PCU_MISC_MODE2) & + (~AR_PCU_MISC_MODE2_HWWAR1); + OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, val); + OS_REG_WRITE(ah, 0x9800 + (651 << 2), 0x11); + } + } /*
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