Date: Tue, 5 Apr 2005 02:23:58 GMT From: Peter Wemm <peter@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 74487 for review Message-ID: <200504050223.j352Nw8l094055@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=74487 Change 74487 by peter@peter_daintree on 2005/04/05 02:23:39 Track i386 changes (mostly inline bus_amd64.h into bus.h) Affected files ... .. //depot/projects/hammer/sys/amd64/amd64/fpu.c#27 integrate .. //depot/projects/hammer/sys/amd64/amd64/machdep.c#121 integrate .. //depot/projects/hammer/sys/amd64/amd64/mp_machdep.c#87 integrate .. //depot/projects/hammer/sys/amd64/amd64/nexus.c#34 integrate .. //depot/projects/hammer/sys/amd64/amd64/sys_machdep.c#18 integrate .. //depot/projects/hammer/sys/amd64/amd64/vm_machdep.c#68 integrate .. //depot/projects/hammer/sys/amd64/conf/GENERIC#69 integrate .. //depot/projects/hammer/sys/amd64/conf/NOTES#60 integrate .. //depot/projects/hammer/sys/amd64/include/bus.h#7 integrate .. //depot/projects/hammer/sys/amd64/include/bus_amd64.h#15 delete .. //depot/projects/hammer/sys/amd64/include/floatingpoint.h#6 integrate .. //depot/projects/hammer/sys/amd64/include/fpu.h#6 integrate .. //depot/projects/hammer/sys/amd64/include/legacyvar.h#9 integrate .. //depot/projects/hammer/sys/amd64/include/md_var.h#30 integrate .. //depot/projects/hammer/sys/amd64/include/pci_cfgreg.h#13 integrate .. //depot/projects/hammer/sys/amd64/include/proc.h#16 integrate .. //depot/projects/hammer/sys/amd64/isa/clock.c#37 integrate .. //depot/projects/hammer/sys/amd64/isa/isa.h#11 integrate .. //depot/projects/hammer/sys/amd64/pci/pci_bus.c#29 integrate Differences ... ==== //depot/projects/hammer/sys/amd64/amd64/fpu.c#27 (text+ko) ==== ==== //depot/projects/hammer/sys/amd64/amd64/machdep.c#121 (text+ko) ==== ==== //depot/projects/hammer/sys/amd64/amd64/mp_machdep.c#87 (text+ko) ==== ==== //depot/projects/hammer/sys/amd64/amd64/nexus.c#34 (text+ko) ==== ==== //depot/projects/hammer/sys/amd64/amd64/sys_machdep.c#18 (text+ko) ==== ==== //depot/projects/hammer/sys/amd64/amd64/vm_machdep.c#68 (text+ko) ==== ==== //depot/projects/hammer/sys/amd64/conf/GENERIC#69 (text+ko) ==== ==== //depot/projects/hammer/sys/amd64/conf/NOTES#60 (text+ko) ==== @@ -4,7 +4,7 @@ # This file contains machine dependent kernel configuration notes. For # machine independent notes, look in /sys/conf/NOTES. # -# (XXX from i386:NOTES,v 1.1188) +# (XXX from i386:NOTES,v 1.1191) # $FreeBSD: src/sys/amd64/conf/NOTES,v 1.27 2005/03/31 20:21:42 scottl Exp $ # @@ -269,6 +269,12 @@ device arcmsr # Areca SATA II RAID # +# Areca 11xx and 12xx series of SATA II RAID controllers. +# CAM is required. +# +device arcmsr # Areca SATA II RAID + +# # 3ware 9000 series PATA/SATA RAID controller driver and options. # The driver is implemented as a SIM, and so, needs the CAM infrastructure. # @@ -571,3 +577,7 @@ # The I/O device device io + +# asr old ioctls support, needed by raidutils + +options ASR_COMPAT ==== //depot/projects/hammer/sys/amd64/include/bus.h#7 (text+ko) ==== @@ -31,10 +31,1228 @@ * $FreeBSD: src/sys/amd64/include/bus.h,v 1.12 2003/05/12 02:44:37 peter Exp $ */ +/* $NetBSD: bus.h,v 1.12 1997/10/01 08:25:15 fvdl Exp $ */ + +/*- + * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, + * NASA Ames Research Center. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by the NetBSD + * Foundation, Inc. and its contributors. + * 4. Neither the name of The NetBSD Foundation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +/*- + * Copyright (c) 1996 Charles M. Hannum. All rights reserved. + * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Christopher G. Demetriou + * for the NetBSD Project. + * 4. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + #ifndef _AMD64_BUS_H_ #define _AMD64_BUS_H_ -#include <machine/bus_amd64.h> +#include <machine/cpufunc.h> + +/* + * To remain compatible with NetBSD's interface, default to both memio and + * pio when neither of them is defined. + */ +#if !defined(_AMD64_BUS_PIO_H_) && !defined(_AMD64_BUS_MEMIO_H_) +#define _AMD64_BUS_PIO_H_ +#define _AMD64_BUS_MEMIO_H_ +#endif + +/* + * Values for the amd64 bus space tag, not to be used directly by MI code. + */ +#define AMD64_BUS_SPACE_IO 0 /* space is i/o space */ +#define AMD64_BUS_SPACE_MEM 1 /* space is mem space */ + +/* + * Bus address and size types + */ +typedef uint64_t bus_addr_t; +typedef uint64_t bus_size_t; + +#define BUS_SPACE_MAXSIZE_24BIT 0xFFFFFF +#define BUS_SPACE_MAXSIZE_32BIT 0xFFFFFFFF +#define BUS_SPACE_MAXSIZE 0xFFFFFFFF +#define BUS_SPACE_MAXADDR_24BIT 0xFFFFFF +#define BUS_SPACE_MAXADDR_32BIT 0xFFFFFFFF +#define BUS_SPACE_MAXADDR 0xFFFFFFFFFFFFFFFFULL + +#define BUS_SPACE_UNRESTRICTED (~0) + +/* + * Access methods for bus resources and address space. + */ +typedef uint64_t bus_space_tag_t; +typedef uint64_t bus_space_handle_t; + +/* + * Map a region of device bus space into CPU virtual address space. + */ + +static __inline int bus_space_map(bus_space_tag_t t, bus_addr_t addr, + bus_size_t size, int flags, + bus_space_handle_t *bshp); + +static __inline int +bus_space_map(bus_space_tag_t t __unused, bus_addr_t addr, + bus_size_t size __unused, int flags __unused, + bus_space_handle_t *bshp) +{ + + *bshp = addr; + return (0); +} + +/* + * Unmap a region of device bus space. + */ + +static __inline void bus_space_unmap(bus_space_tag_t t, bus_space_handle_t bsh, + bus_size_t size); + +static __inline void +bus_space_unmap(bus_space_tag_t t __unused, bus_space_handle_t bsh __unused, + bus_size_t size __unused) +{ +} + +/* + * Get a new handle for a subregion of an already-mapped area of bus space. + */ + +static __inline int bus_space_subregion(bus_space_tag_t t, + bus_space_handle_t bsh, + bus_size_t offset, bus_size_t size, + bus_space_handle_t *nbshp); + +static __inline int +bus_space_subregion(bus_space_tag_t t __unused, bus_space_handle_t bsh, + bus_size_t offset, bus_size_t size __unused, + bus_space_handle_t *nbshp) +{ + + *nbshp = bsh + offset; + return (0); +} + +/* + * Allocate a region of memory that is accessible to devices in bus space. + */ + +int bus_space_alloc(bus_space_tag_t t, bus_addr_t rstart, + bus_addr_t rend, bus_size_t size, bus_size_t align, + bus_size_t boundary, int flags, bus_addr_t *addrp, + bus_space_handle_t *bshp); + +/* + * Free a region of bus space accessible memory. + */ + +static __inline void bus_space_free(bus_space_tag_t t, bus_space_handle_t bsh, + bus_size_t size); + +static __inline void +bus_space_free(bus_space_tag_t t __unused, bus_space_handle_t bsh __unused, + bus_size_t size __unused) +{ +} + + +#if defined(_AMD64_BUS_PIO_H_) || defined(_AMD64_BUS_MEMIO_H_) + +/* + * Read a 1, 2, 4, or 8 byte quantity from bus space + * described by tag/handle/offset. + */ +static __inline u_int8_t bus_space_read_1(bus_space_tag_t tag, + bus_space_handle_t handle, + bus_size_t offset); + +static __inline u_int16_t bus_space_read_2(bus_space_tag_t tag, + bus_space_handle_t handle, + bus_size_t offset); + +static __inline u_int32_t bus_space_read_4(bus_space_tag_t tag, + bus_space_handle_t handle, + bus_size_t offset); + +static __inline u_int8_t +bus_space_read_1(bus_space_tag_t tag, bus_space_handle_t handle, + bus_size_t offset) +{ +#if defined (_AMD64_BUS_PIO_H_) +#if defined (_AMD64_BUS_MEMIO_H_) + if (tag == AMD64_BUS_SPACE_IO) +#endif + return (inb(handle + offset)); +#endif +#if defined (_AMD64_BUS_MEMIO_H_) + return (*(volatile u_int8_t *)(handle + offset)); +#endif +} + +static __inline u_int16_t +bus_space_read_2(bus_space_tag_t tag, bus_space_handle_t handle, + bus_size_t offset) +{ +#if defined(_AMD64_BUS_PIO_H_) +#if defined(_AMD64_BUS_MEMIO_H_) + if (tag == AMD64_BUS_SPACE_IO) +#endif + return (inw(handle + offset)); +#endif +#if defined(_AMD64_BUS_MEMIO_H_) + return (*(volatile u_int16_t *)(handle + offset)); +#endif +} + +static __inline u_int32_t +bus_space_read_4(bus_space_tag_t tag, bus_space_handle_t handle, + bus_size_t offset) +{ +#if defined(_AMD64_BUS_PIO_H_) +#if defined(_AMD64_BUS_MEMIO_H_) + if (tag == AMD64_BUS_SPACE_IO) +#endif + return (inl(handle + offset)); +#endif +#if defined(_AMD64_BUS_MEMIO_H_) + return (*(volatile u_int32_t *)(handle + offset)); +#endif +} + +#if 0 /* Cause a link error for bus_space_read_8 */ +#define bus_space_read_8(t, h, o) !!! bus_space_read_8 unimplemented !!! +#endif + +/* + * Read `count' 1, 2, 4, or 8 byte quantities from bus space + * described by tag/handle/offset and copy into buffer provided. + */ +static __inline void bus_space_read_multi_1(bus_space_tag_t tag, + bus_space_handle_t bsh, + bus_size_t offset, u_int8_t *addr, + size_t count); + +static __inline void bus_space_read_multi_2(bus_space_tag_t tag, + bus_space_handle_t bsh, + bus_size_t offset, u_int16_t *addr, + size_t count); + +static __inline void bus_space_read_multi_4(bus_space_tag_t tag, + bus_space_handle_t bsh, + bus_size_t offset, u_int32_t *addr, + size_t count); + +static __inline void +bus_space_read_multi_1(bus_space_tag_t tag, bus_space_handle_t bsh, + bus_size_t offset, u_int8_t *addr, size_t count) +{ +#if defined(_AMD64_BUS_PIO_H_) +#if defined(_AMD64_BUS_MEMIO_H_) + if (tag == AMD64_BUS_SPACE_IO) +#endif + insb(bsh + offset, addr, count); +#endif +#if defined(_AMD64_BUS_MEMIO_H_) +#if defined(_AMD64_BUS_PIO_H_) + else +#endif + { +#ifdef __GNUCLIKE_ASM + __asm __volatile(" \n\ + cld \n\ + 1: movb (%2),%%al \n\ + stosb \n\ + loop 1b" : + "=D" (addr), "=c" (count) : + "r" (bsh + offset), "0" (addr), "1" (count) : + "%eax", "memory"); +#endif + } +#endif +} + +static __inline void +bus_space_read_multi_2(bus_space_tag_t tag, bus_space_handle_t bsh, + bus_size_t offset, u_int16_t *addr, size_t count) +{ +#if defined(_AMD64_BUS_PIO_H_) +#if defined(_AMD64_BUS_MEMIO_H_) + if (tag == AMD64_BUS_SPACE_IO) +#endif + insw(bsh + offset, addr, count); +#endif +#if defined(_AMD64_BUS_MEMIO_H_) +#if defined(_AMD64_BUS_PIO_H_) + else +#endif + { +#ifdef __GNUCLIKE_ASM + __asm __volatile(" \n\ + cld \n\ + 1: movw (%2),%%ax \n\ + stosw \n\ + loop 1b" : + "=D" (addr), "=c" (count) : + "r" (bsh + offset), "0" (addr), "1" (count) : + "%eax", "memory"); +#endif + } +#endif +} + +static __inline void +bus_space_read_multi_4(bus_space_tag_t tag, bus_space_handle_t bsh, + bus_size_t offset, u_int32_t *addr, size_t count) +{ +#if defined(_AMD64_BUS_PIO_H_) +#if defined(_AMD64_BUS_MEMIO_H_) + if (tag == AMD64_BUS_SPACE_IO) +#endif + insl(bsh + offset, addr, count); +#endif +#if defined(_AMD64_BUS_MEMIO_H_) +#if defined(_AMD64_BUS_PIO_H_) + else +#endif + { +#ifdef __GNUCLIKE_ASM + __asm __volatile(" \n\ + cld \n\ + 1: movl (%2),%%eax \n\ + stosl \n\ + loop 1b" : + "=D" (addr), "=c" (count) : + "r" (bsh + offset), "0" (addr), "1" (count) : + "%eax", "memory"); +#endif + } +#endif +} + +#if 0 /* Cause a link error for bus_space_read_multi_8 */ +#define bus_space_read_multi_8 !!! bus_space_read_multi_8 unimplemented !!! +#endif + +/* + * Read `count' 1, 2, 4, or 8 byte quantities from bus space + * described by tag/handle and starting at `offset' and copy into + * buffer provided. + */ +static __inline void bus_space_read_region_1(bus_space_tag_t tag, + bus_space_handle_t bsh, + bus_size_t offset, u_int8_t *addr, + size_t count); + +static __inline void bus_space_read_region_2(bus_space_tag_t tag, + bus_space_handle_t bsh, + bus_size_t offset, u_int16_t *addr, + size_t count); + +static __inline void bus_space_read_region_4(bus_space_tag_t tag, + bus_space_handle_t bsh, + bus_size_t offset, u_int32_t *addr, + size_t count); + + +static __inline void +bus_space_read_region_1(bus_space_tag_t tag, bus_space_handle_t bsh, + bus_size_t offset, u_int8_t *addr, size_t count) +{ +#if defined(_AMD64_BUS_PIO_H_) +#if defined(_AMD64_BUS_MEMIO_H_) + if (tag == AMD64_BUS_SPACE_IO) +#endif + { + int _port_ = bsh + offset; +#ifdef __GNUCLIKE_ASM + __asm __volatile(" \n\ + cld \n\ + 1: inb %w2,%%al \n\ + stosb \n\ + incl %2 \n\ + loop 1b" : + "=D" (addr), "=c" (count), "=d" (_port_) : + "0" (addr), "1" (count), "2" (_port_) : + "%eax", "memory", "cc"); +#endif + } +#endif +#if defined(_AMD64_BUS_MEMIO_H_) +#if defined(_AMD64_BUS_PIO_H_) + else +#endif + { + bus_space_handle_t _port_ = bsh + offset; +#ifdef __GNUCLIKE_ASM + __asm __volatile(" \n\ + cld \n\ + repne \n\ + movsb" : + "=D" (addr), "=c" (count), "=S" (_port_) : + "0" (addr), "1" (count), "2" (_port_) : + "memory", "cc"); +#endif + } +#endif +} + +static __inline void +bus_space_read_region_2(bus_space_tag_t tag, bus_space_handle_t bsh, + bus_size_t offset, u_int16_t *addr, size_t count) +{ +#if defined(_AMD64_BUS_PIO_H_) +#if defined(_AMD64_BUS_MEMIO_H_) + if (tag == AMD64_BUS_SPACE_IO) +#endif + { + int _port_ = bsh + offset; +#ifdef __GNUCLIKE_ASM + __asm __volatile(" \n\ + cld \n\ + 1: inw %w2,%%ax \n\ + stosw \n\ + addl $2,%2 \n\ + loop 1b" : + "=D" (addr), "=c" (count), "=d" (_port_) : + "0" (addr), "1" (count), "2" (_port_) : + "%eax", "memory", "cc"); +#endif + } +#endif +#if defined(_AMD64_BUS_MEMIO_H_) +#if defined(_AMD64_BUS_PIO_H_) + else +#endif + { + bus_space_handle_t _port_ = bsh + offset; +#ifdef __GNUCLIKE_ASM + __asm __volatile(" \n\ + cld \n\ + repne \n\ + movsw" : + "=D" (addr), "=c" (count), "=S" (_port_) : + "0" (addr), "1" (count), "2" (_port_) : + "memory", "cc"); +#endif + } +#endif +} + +static __inline void +bus_space_read_region_4(bus_space_tag_t tag, bus_space_handle_t bsh, + bus_size_t offset, u_int32_t *addr, size_t count) +{ +#if defined(_AMD64_BUS_PIO_H_) +#if defined(_AMD64_BUS_MEMIO_H_) + if (tag == AMD64_BUS_SPACE_IO) +#endif + { + int _port_ = bsh + offset; +#ifdef __GNUCLIKE_ASM + __asm __volatile(" \n\ + cld \n\ + 1: inl %w2,%%eax \n\ + stosl \n\ + addl $4,%2 \n\ + loop 1b" : + "=D" (addr), "=c" (count), "=d" (_port_) : + "0" (addr), "1" (count), "2" (_port_) : + "%eax", "memory", "cc"); +#endif + } +#endif +#if defined(_AMD64_BUS_MEMIO_H_) +#if defined(_AMD64_BUS_PIO_H_) + else +#endif + { + bus_space_handle_t _port_ = bsh + offset; +#ifdef __GNUCLIKE_ASM + __asm __volatile(" \n\ + cld \n\ + repne \n\ + movsl" : + "=D" (addr), "=c" (count), "=S" (_port_) : + "0" (addr), "1" (count), "2" (_port_) : + "memory", "cc"); +#endif + } +#endif +} + +#if 0 /* Cause a link error for bus_space_read_region_8 */ +#define bus_space_read_region_8 !!! bus_space_read_region_8 unimplemented !!! +#endif + +/* + * Write the 1, 2, 4, or 8 byte value `value' to bus space + * described by tag/handle/offset. + */ + +static __inline void bus_space_write_1(bus_space_tag_t tag, + bus_space_handle_t bsh, + bus_size_t offset, u_int8_t value); + +static __inline void bus_space_write_2(bus_space_tag_t tag, + bus_space_handle_t bsh, + bus_size_t offset, u_int16_t value); + +static __inline void bus_space_write_4(bus_space_tag_t tag, + bus_space_handle_t bsh, + bus_size_t offset, u_int32_t value); + +static __inline void +bus_space_write_1(bus_space_tag_t tag, bus_space_handle_t bsh, + bus_size_t offset, u_int8_t value) +{ +#if defined(_AMD64_BUS_PIO_H_) +#if defined(_AMD64_BUS_MEMIO_H_) + if (tag == AMD64_BUS_SPACE_IO) +#endif + outb(bsh + offset, value); +#endif +#if defined(_AMD64_BUS_MEMIO_H_) +#if defined(_AMD64_BUS_PIO_H_) + else +#endif + *(volatile u_int8_t *)(bsh + offset) = value; +#endif +} + +static __inline void +bus_space_write_2(bus_space_tag_t tag, bus_space_handle_t bsh, + bus_size_t offset, u_int16_t value) +{ +#if defined(_AMD64_BUS_PIO_H_) +#if defined(_AMD64_BUS_MEMIO_H_) + if (tag == AMD64_BUS_SPACE_IO) +#endif + outw(bsh + offset, value); +#endif +#if defined(_AMD64_BUS_MEMIO_H_) +#if defined(_AMD64_BUS_PIO_H_) + else +#endif + *(volatile u_int16_t *)(bsh + offset) = value; +#endif +} + +static __inline void +bus_space_write_4(bus_space_tag_t tag, bus_space_handle_t bsh, + bus_size_t offset, u_int32_t value) +{ +#if defined(_AMD64_BUS_PIO_H_) +#if defined(_AMD64_BUS_MEMIO_H_) + if (tag == AMD64_BUS_SPACE_IO) +#endif + outl(bsh + offset, value); +#endif +#if defined(_AMD64_BUS_MEMIO_H_) +#if defined(_AMD64_BUS_PIO_H_) + else +#endif + *(volatile u_int32_t *)(bsh + offset) = value; +#endif +} + +#if 0 /* Cause a link error for bus_space_write_8 */ +#define bus_space_write_8 !!! bus_space_write_8 not implemented !!! +#endif + +/* + * Write `count' 1, 2, 4, or 8 byte quantities from the buffer + * provided to bus space described by tag/handle/offset. + */ + +static __inline void bus_space_write_multi_1(bus_space_tag_t tag, + bus_space_handle_t bsh, + bus_size_t offset, + const u_int8_t *addr, + size_t count); +static __inline void bus_space_write_multi_2(bus_space_tag_t tag, + bus_space_handle_t bsh, + bus_size_t offset, + const u_int16_t *addr, + size_t count); + +static __inline void bus_space_write_multi_4(bus_space_tag_t tag, + bus_space_handle_t bsh, + bus_size_t offset, + const u_int32_t *addr, + size_t count); + +static __inline void +bus_space_write_multi_1(bus_space_tag_t tag, bus_space_handle_t bsh, + bus_size_t offset, const u_int8_t *addr, size_t count) +{ +#if defined(_AMD64_BUS_PIO_H_) +#if defined(_AMD64_BUS_MEMIO_H_) + if (tag == AMD64_BUS_SPACE_IO) +#endif + outsb(bsh + offset, addr, count); +#endif +#if defined(_AMD64_BUS_MEMIO_H_) +#if defined(_AMD64_BUS_PIO_H_) + else +#endif + { +#ifdef __GNUCLIKE_ASM + __asm __volatile(" \n\ + cld \n\ + 1: lodsb \n\ + movb %%al,(%2) \n\ + loop 1b" : + "=S" (addr), "=c" (count) : + "r" (bsh + offset), "0" (addr), "1" (count) : + "%eax", "memory", "cc"); +#endif + } +#endif +} + +static __inline void +bus_space_write_multi_2(bus_space_tag_t tag, bus_space_handle_t bsh, + bus_size_t offset, const u_int16_t *addr, size_t count) +{ +#if defined(_AMD64_BUS_PIO_H_) +#if defined(_AMD64_BUS_MEMIO_H_) + if (tag == AMD64_BUS_SPACE_IO) +#endif + outsw(bsh + offset, addr, count); +#endif +#if defined(_AMD64_BUS_MEMIO_H_) +#if defined(_AMD64_BUS_PIO_H_) + else +#endif + { +#ifdef __GNUCLIKE_ASM + __asm __volatile(" \n\ + cld \n\ + 1: lodsw \n\ + movw %%ax,(%2) \n\ + loop 1b" : + "=S" (addr), "=c" (count) : + "r" (bsh + offset), "0" (addr), "1" (count) : + "%eax", "memory", "cc"); +#endif + } +#endif +} + +static __inline void +bus_space_write_multi_4(bus_space_tag_t tag, bus_space_handle_t bsh, + bus_size_t offset, const u_int32_t *addr, size_t count) +{ +#if defined(_AMD64_BUS_PIO_H_) +#if defined(_AMD64_BUS_MEMIO_H_) + if (tag == AMD64_BUS_SPACE_IO) +#endif + outsl(bsh + offset, addr, count); +#endif +#if defined(_AMD64_BUS_MEMIO_H_) +#if defined(_AMD64_BUS_PIO_H_) + else +#endif + { +#ifdef __GNUCLIKE_ASM + __asm __volatile(" \n\ + cld \n\ + 1: lodsl \n\ + movl %%eax,(%2) \n\ + loop 1b" : + "=S" (addr), "=c" (count) : + "r" (bsh + offset), "0" (addr), "1" (count) : + "%eax", "memory", "cc"); +#endif + } +#endif +} + +#if 0 /* Cause a link error for bus_space_write_multi_8 */ +#define bus_space_write_multi_8(t, h, o, a, c) \ + !!! bus_space_write_multi_8 unimplemented !!! +#endif + +/* + * Write `count' 1, 2, 4, or 8 byte quantities from the buffer provided + * to bus space described by tag/handle starting at `offset'. + */ + +static __inline void bus_space_write_region_1(bus_space_tag_t tag, + bus_space_handle_t bsh, + bus_size_t offset, + const u_int8_t *addr, + size_t count); +static __inline void bus_space_write_region_2(bus_space_tag_t tag, + bus_space_handle_t bsh, + bus_size_t offset, + const u_int16_t *addr, + size_t count); +static __inline void bus_space_write_region_4(bus_space_tag_t tag, + bus_space_handle_t bsh, + bus_size_t offset, + const u_int32_t *addr, + size_t count); + +static __inline void +bus_space_write_region_1(bus_space_tag_t tag, bus_space_handle_t bsh, + bus_size_t offset, const u_int8_t *addr, size_t count) +{ +#if defined(_AMD64_BUS_PIO_H_) +#if defined(_AMD64_BUS_MEMIO_H_) + if (tag == AMD64_BUS_SPACE_IO) +#endif + { + int _port_ = bsh + offset; +#ifdef __GNUCLIKE_ASM + __asm __volatile(" \n\ + cld \n\ + 1: lodsb \n\ + outb %%al,%w0 \n\ + incl %0 \n\ + loop 1b" : + "=d" (_port_), "=S" (addr), "=c" (count) : + "0" (_port_), "1" (addr), "2" (count) : + "%eax", "memory", "cc"); +#endif + } +#endif +#if defined(_AMD64_BUS_MEMIO_H_) +#if defined(_AMD64_BUS_PIO_H_) + else +#endif + { + bus_space_handle_t _port_ = bsh + offset; +#ifdef __GNUCLIKE_ASM + __asm __volatile(" \n\ + cld \n\ + repne \n\ + movsb" : + "=D" (_port_), "=S" (addr), "=c" (count) : + "0" (_port_), "1" (addr), "2" (count) : + "memory", "cc"); +#endif + } +#endif +} + +static __inline void +bus_space_write_region_2(bus_space_tag_t tag, bus_space_handle_t bsh, + bus_size_t offset, const u_int16_t *addr, size_t count) +{ +#if defined(_AMD64_BUS_PIO_H_) +#if defined(_AMD64_BUS_MEMIO_H_) + if (tag == AMD64_BUS_SPACE_IO) +#endif + { + int _port_ = bsh + offset; +#ifdef __GNUCLIKE_ASM + __asm __volatile(" \n\ + cld \n\ + 1: lodsw \n\ + outw %%ax,%w0 \n\ + addl $2,%0 \n\ + loop 1b" : + "=d" (_port_), "=S" (addr), "=c" (count) : + "0" (_port_), "1" (addr), "2" (count) : + "%eax", "memory", "cc"); +#endif + } +#endif +#if defined(_AMD64_BUS_MEMIO_H_) +#if defined(_AMD64_BUS_PIO_H_) + else +#endif + { + bus_space_handle_t _port_ = bsh + offset; +#ifdef __GNUCLIKE_ASM + __asm __volatile(" \n\ + cld \n\ + repne \n\ + movsw" : + "=D" (_port_), "=S" (addr), "=c" (count) : + "0" (_port_), "1" (addr), "2" (count) : + "memory", "cc"); +#endif + } +#endif +} + +static __inline void +bus_space_write_region_4(bus_space_tag_t tag, bus_space_handle_t bsh, + bus_size_t offset, const u_int32_t *addr, size_t count) +{ +#if defined(_AMD64_BUS_PIO_H_) +#if defined(_AMD64_BUS_MEMIO_H_) + if (tag == AMD64_BUS_SPACE_IO) +#endif + { + int _port_ = bsh + offset; +#ifdef __GNUCLIKE_ASM + __asm __volatile(" \n\ + cld \n\ + 1: lodsl \n\ + outl %%eax,%w0 \n\ + addl $4,%0 \n\ + loop 1b" : + "=d" (_port_), "=S" (addr), "=c" (count) : + "0" (_port_), "1" (addr), "2" (count) : + "%eax", "memory", "cc"); +#endif + } +#endif +#if defined(_AMD64_BUS_MEMIO_H_) +#if defined(_AMD64_BUS_PIO_H_) + else +#endif + { + bus_space_handle_t _port_ = bsh + offset; +#ifdef __GNUCLIKE_ASM + __asm __volatile(" \n\ + cld \n\ + repne \n\ + movsl" : + "=D" (_port_), "=S" (addr), "=c" (count) : + "0" (_port_), "1" (addr), "2" (count) : + "memory", "cc"); +#endif + } +#endif +} + +#if 0 /* Cause a link error for bus_space_write_region_8 */ +#define bus_space_write_region_8 \ + !!! bus_space_write_region_8 unimplemented !!! +#endif + +/* + * Write the 1, 2, 4, or 8 byte value `val' to bus space described + * by tag/handle/offset `count' times. + */ + +static __inline void bus_space_set_multi_1(bus_space_tag_t tag, + bus_space_handle_t bsh, + bus_size_t offset, + u_int8_t value, size_t count); +static __inline void bus_space_set_multi_2(bus_space_tag_t tag, + bus_space_handle_t bsh, + bus_size_t offset, + u_int16_t value, size_t count); +static __inline void bus_space_set_multi_4(bus_space_tag_t tag, + bus_space_handle_t bsh, + bus_size_t offset, + u_int32_t value, size_t count); + +static __inline void +bus_space_set_multi_1(bus_space_tag_t tag, bus_space_handle_t bsh, + bus_size_t offset, u_int8_t value, size_t count) +{ + bus_space_handle_t addr = bsh + offset; + +#if defined(_AMD64_BUS_PIO_H_) +#if defined(_AMD64_BUS_MEMIO_H_) + if (tag == AMD64_BUS_SPACE_IO) +#endif + while (count--) + outb(addr, value); +#endif +#if defined(_AMD64_BUS_MEMIO_H_) +#if defined(_AMD64_BUS_PIO_H_) + else +#endif + while (count--) + *(volatile u_int8_t *)(addr) = value; +#endif +} + +static __inline void +bus_space_set_multi_2(bus_space_tag_t tag, bus_space_handle_t bsh, + bus_size_t offset, u_int16_t value, size_t count) +{ + bus_space_handle_t addr = bsh + offset; + +#if defined(_AMD64_BUS_PIO_H_) +#if defined(_AMD64_BUS_MEMIO_H_) + if (tag == AMD64_BUS_SPACE_IO) +#endif + while (count--) + outw(addr, value); +#endif +#if defined(_AMD64_BUS_MEMIO_H_) +#if defined(_AMD64_BUS_PIO_H_) + else +#endif + while (count--) >>> TRUNCATED FOR MAIL (1000 lines) <<<
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