Date: Fri, 4 Jan 2008 07:45:16 GMT From: Warner Losh <imp@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 132463 for review Message-ID: <200801040745.m047jG0v051327@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=132463 Change 132463 by imp@imp_paco-paco on 2008/01/04 07:44:17 Resolve all the multiple definitions. We go from ~10,000 lines of output on the link down to 117. There's about 60 undefined symbols now. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/conf/files.mips#4 edit .. //depot/projects/mips2-jnpr/src/sys/mips/include/cpu.h#7 edit .. //depot/projects/mips2-jnpr/src/sys/mips/include/intr.h#4 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips/cpu.c#4 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips/interrupt.c#4 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips/machdep.c#6 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips/sys_machdep.c#2 delete Differences ... ==== //depot/projects/mips2-jnpr/src/sys/conf/files.mips#4 (text+ko) ==== @@ -81,7 +81,6 @@ mips/mips/stack_machdep.c optional ddb | stack mips/mips/support.S standard mips/mips/swtch.S standard -mips/mips/sys_machdep.c standard mips/mips/tick.c standard mips/mips/uio_machdep.c standard geom/geom_bsd.c standard @@ -91,7 +90,6 @@ libkern/ashldi3.c standard libkern/ashrdi3.c standard libkern/divdi3.c standard -libkern/ffs.c standard libkern/ffsl.c standard libkern/fls.c standard libkern/flsl.c standard ==== //depot/projects/mips2-jnpr/src/sys/mips/include/cpu.h#7 (text+ko) ==== @@ -430,36 +430,36 @@ #define MIPS_VR5400 0x54 /* NEC Vr5400 FPU ISA IV+ */ #ifndef _LOCORE -union cpuprid cpu_id; +extern union cpuprid cpu_id; #define mips_proc_type() ((cpu_id.cpu.cp_vendor << 8) | cpu_id.cpu.cp_imp) #define mips_set_proc_type(type) (cpu_id.cpu.cp_vendor = (type) >> 8, \ cpu_id.cpu.cp_imp = ((type) & 0x00ff)) #endif /* !_LOCORE */ #if defined(_KERNEL) && !defined(_LOCORE) -union cpuprid fpu_id; +extern union cpuprid fpu_id; -u_int CpuPrimaryInstCacheSize; -u_int CpuPrimaryInstCacheLSize; -u_int CpuPrimaryInstSetSize; -u_int CpuPrimaryInstCacheNsets; -u_int CpuPrimaryInstCacheAsso; +extern u_int CpuPrimaryInstCacheSize; +extern u_int CpuPrimaryInstCacheLSize; +extern u_int CpuPrimaryInstSetSize; +extern u_int CpuPrimaryInstCacheNsets; +extern u_int CpuPrimaryInstCacheAsso; -u_int CpuPrimaryDataCacheSize; -u_int CpuPrimaryDataCacheLSize; -u_int CpuPrimaryDataSetSize; -u_int CpuPrimaryDataCacheNsets; -u_int CpuPrimaryDataCacheAsso; +extern u_int CpuPrimaryDataCacheSize; +extern u_int CpuPrimaryDataCacheLSize; +extern u_int CpuPrimaryDataSetSize; +extern u_int CpuPrimaryDataCacheNsets; +extern u_int CpuPrimaryDataCacheAsso; -u_int CpuCacheAliasMask; -u_int CpuSecondaryCacheSize; -u_int CpuTertiaryCacheSize; -u_int CpuNWayCache; -u_int CpuCacheType; -u_int CpuConfigRegister; -u_int CpuStatusRegister; -u_int CpuExternalCacheOn; -u_int CpuOnboardCacheOn; +extern u_int CpuCacheAliasMask; +extern u_int CpuSecondaryCacheSize; +extern u_int CpuTertiaryCacheSize; +extern u_int CpuNWayCache; +extern u_int CpuCacheType; +extern u_int CpuConfigRegister; +extern u_int CpuStatusRegister; +extern u_int CpuExternalCacheOn; +extern u_int CpuOnboardCacheOn; struct tlb; struct user; ==== //depot/projects/mips2-jnpr/src/sys/mips/include/intr.h#4 (text+ko) ==== @@ -53,8 +53,8 @@ #define INTRCNT_PE 3 /* irq 4 */ #define INTRCNT_PICNIC 4 /* irq 5 */ -intrmask_t idle_mask; -void (*mips_ack_interrupt)(int, intrmask_t); +extern intrmask_t idle_mask; +extern void (*mips_ack_interrupt)(int, intrmask_t); typedef int ih_func_t(void *); @@ -71,7 +71,7 @@ void *frame; }; -struct mips_intr_handler intr_handlers[16]; +extern struct mips_intr_handler intr_handlers[]; struct trapframe; void mips_set_intr(int pri, intrmask_t mask, ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/cpu.c#4 (text+ko) ==== @@ -40,6 +40,30 @@ #include <sys/module.h> #include <machine/bus.h> +union cpuprid cpu_id; +union cpuprid fpu_id; + +u_int CpuPrimaryInstCacheSize; +u_int CpuPrimaryInstCacheLSize; +u_int CpuPrimaryInstSetSize; +u_int CpuPrimaryInstCacheNsets; +u_int CpuPrimaryInstCacheAsso; + +u_int CpuPrimaryDataCacheSize; +u_int CpuPrimaryDataCacheLSize; +u_int CpuPrimaryDataSetSize; +u_int CpuPrimaryDataCacheNsets; +u_int CpuPrimaryDataCacheAsso; + +u_int CpuCacheAliasMask; +u_int CpuSecondaryCacheSize; +u_int CpuTertiaryCacheSize; +u_int CpuNWayCache; +u_int CpuCacheType; +u_int CpuConfigRegister; +u_int CpuStatusRegister; +u_int CpuExternalCacheOn; +u_int CpuOnboardCacheOn; static void cpu_identify(driver_t *driver, device_t parent); static int cpu_probe(device_t dev); ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/interrupt.c#4 (text+ko) ==== @@ -70,6 +70,10 @@ #include <machine/archtype.h> #include <machine/asm.h> +intrmask_t idle_mask; +void (*mips_ack_interrupt)(int, intrmask_t); +struct mips_intr_handler intr_handlers[16]; + /* * Modern versions of MIPS processors have extended interrupt * capabilites. How these are handeled differs from implementation ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/machdep.c#6 (text+ko) ====help
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