Date: Tue, 19 Jul 2022 07:37:16 GMT From: Andrew Turner <andrew@FreeBSD.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-branches@FreeBSD.org Subject: git: c41c04043fc6 - stable/13 - Decode all Arm GIC feature ID bits Message-ID: <202207190737.26J7bGK3021378@gitrepo.freebsd.org>
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The branch stable/13 has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=c41c04043fc6ee9e8197ddd9e90a2325f8c4f5c1 commit c41c04043fc6ee9e8197ddd9e90a2325f8c4f5c1 Author: Andrew Turner <andrew@FreeBSD.org> AuthorDate: 2022-05-24 10:03:13 +0000 Commit: Andrew Turner <andrew@FreeBSD.org> CommitDate: 2022-07-19 07:03:30 +0000 Decode all Arm GIC feature ID bits The AWS Graviton3 CPU features a GIC 4.1 CPU Interface. Teach the CPU identift code to decode it. Sponsored by: The FreeBSD Foundation (cherry picked from commit 477204e70b658c518064a02203a2050d5a0841be) --- sys/arm64/arm64/identcpu.c | 3 +++ sys/arm64/include/armreg.h | 1 + 2 files changed, 4 insertions(+) diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c index af5ed5dfb969..514671837015 100644 --- a/sys/arm64/arm64/identcpu.c +++ b/sys/arm64/arm64/identcpu.c @@ -1108,6 +1108,9 @@ static struct mrs_field_value id_aa64pfr0_ras[] = { static struct mrs_field_value id_aa64pfr0_gic[] = { MRS_FIELD_VALUE_NONE_IMPL(ID_AA64PFR0, GIC, CPUIF_NONE, CPUIF_EN), + MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_NONE, ""), + MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_EN, "GIC"), + MRS_FIELD_VALUE(ID_AA64PFR0_GIC_CPUIF_4_1, "GIC 4.1"), MRS_FIELD_VALUE_END, }; diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 1e7982a101c5..4c752ea24ab6 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -828,6 +828,7 @@ #define ID_AA64PFR0_GIC_VAL(x) ((x) & ID_AA64PFR0_GIC_MASK) #define ID_AA64PFR0_GIC_CPUIF_NONE (UL(0x0) << ID_AA64PFR0_GIC_SHIFT) #define ID_AA64PFR0_GIC_CPUIF_EN (UL(0x1) << ID_AA64PFR0_GIC_SHIFT) +#define ID_AA64PFR0_GIC_CPUIF_4_1 (UL(0x3) << ID_AA64PFR0_GIC_SHIFT) #define ID_AA64PFR0_RAS_SHIFT 28 #define ID_AA64PFR0_RAS_MASK (UL(0xf) << ID_AA64PFR0_RAS_SHIFT) #define ID_AA64PFR0_RAS_VAL(x) ((x) & ID_AA64PFR0_RAS_MASK)
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