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Date:      Sat, 12 Jun 2010 01:45:29 +0000 (UTC)
From:      Marcel Moolenaar <marcel@FreeBSD.org>
To:        cvs-src-old@freebsd.org
Subject:   cvs commit: src/sys/ia64/ia64 exception.S pmap.c
Message-ID:  <201006120145.o5C1jmko016407@repoman.freebsd.org>

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marcel      2010-06-12 01:45:29 UTC

  FreeBSD src repository

  Modified files:
    sys/ia64/ia64        exception.S pmap.c 
  Log:
  SVN rev 209085 on 2010-06-12 01:45:29Z by marcel
  
  The ptc.g operation for the Mckinley and Madison processors has the
  side-effect of purging more than the requested translation. While
  this is not a problem in general, it invalidates the assumption made
  during constructing the trapframe on entry into the kernel in SMP
  configurations. The assumption is that only the first store to the
  stack will possibly cause a TLB miss. Since the ptc.g purges the
  translation caches of all CPUs in the coherency domain, a ptc.g
  executed on one CPU can cause a purge on another CPU that is
  currently running the critical code that saves the state to the
  trapframe. This can cause an unexpected TLB miss and with interrupt
  collection disabled this means an unexpected data nested TLB fault.
  
  A data nested TLB fault will not save any context, nor provide a
  way for software to determine what caused the TLB miss nor where
  it occured. Careful construction of the kernel entry and exit code
  allows us to handle a TLB miss in precisely orchastrated points
  and thereby avoiding the need to wire the kernel stack, but the
  unexpected TLB miss caused by the ptc.g instructution resulted in
  an unrecoverable condition and resulting in machine checks.
  
  The solution to this problem is to synchronize the kernel entry
  on all CPUs with the use of the ptc.g instruction on a single CPU
  by implementing a bare-bones readers-writer lock that allows N
  readers (= N CPUs entering the kernel) and 1 writer (= execution
  of the ptc.g instruction on some CPU). This solution wins over
  a rendez-vous approach by not interrupting CPUs with an IPI.
  
  This problem has not been observed on the Montecito.
  
  PR:             ia64/147772
  MFC after:      6 days
  
  Revision  Changes    Path
  1.72      +38 -0     src/sys/ia64/ia64/exception.S
  1.225     +29 -6     src/sys/ia64/ia64/pmap.c



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