Date: Sat, 26 Oct 2013 01:22:24 +0200 From: Zbigniew Bodek <zbb@freebsd.org> To: "freebsd-arm@freebsd.org" <freebsd-arm@freebsd.org> Cc: Kevin Lo <kevlo@freebsd.org> Subject: Re: Changes to Armada XP Message-ID: <CALF_TxmJRanYd=sq5dHUXoJMUnkHy0aVssxV4KCVaxa%2BiBjERw@mail.gmail.com> In-Reply-To: <52536AD4.4070603@FreeBSD.org> References: <CALF_TxnejdzhrGURPUKGg1BiAi_DVUWVR5vrJsXkN%2BKz6uJvzw@mail.gmail.com> <52536AD4.4070603@FreeBSD.org>
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[-- Attachment #1 --]
Hello again.
Apart from the earlier mentioned patches I would like to add some more:
0004 - some clean-ups to generic ARM code related to AXP
0005 - some AXP based boards have different SoC registers' base
address so we need to
correct configuration variables and eventually DT to map
this properly and
boot without problems on any type of u-boot.
0006 - just modifying the kernel load address. If I commit this I will
change the entry on AXP wiki page accordingly.
0007 - removal of the obsolete PJ4Bv6 code
0008 - disabling explicit TLB broadcasting using IPI. PJ4Bv7 is
capable of doing this in HW
More detailed descriptions are of course in commit-logs.
Please test those patches if you like and send your remarks if there are any.
I would like to commit this (and previous patches) by the end of Saturday 26th
because I'm stashing this for quite some time now.
So if there will be no objections I will do as described :)
Thank you and best regards
Zbigniew Bodek
2013/10/8 Kevin Lo <kevlo@freebsd.org>:
> Zbigniew Bodek wrote:
>>
>> Hello.
>>
>> I would like to commit two patches for Armada XP.
>>
>> 0002 - is enabling busy-detection for UART on Armada XP. Combined with
>> another patch for ns8250 UART (posted in the separate e-mail) this fixes
>> UART IF issues on Armada XP.
>>
>> 0003 - enables SATA interface on Armada XP.
>>
>> If there are no objections then I would like to commit them in the near
>> future.
>
>
> Works for me. Tested on the Openblocks AX3. Thanks!
>
>>
>> Best regards
>> Zbigniew Bodek
>
>
> Kevin
[-- Attachment #2 --]
From 030d72310c4b00d2b997aaf23a1496a49ee0d545 Mon Sep 17 00:00:00 2001
From: Zbigniew Bodek <zbb@semihalf.com>
Date: Sat, 12 Oct 2013 00:06:05 +0200
Subject: [PATCH 4/8] Remove hard-coded mappings related to Armada XP support
Armada XP initialization flow requires SoC registers to be
mapped very early in order to configure Snoop Filter for SMP.
Additional mapping in locore.S is redundant as proper mapping is
made in pmap_devmap_bootstrap() prior to calling cpu_setup() which
configures the Snoop Filter.
For secondaru CPUs it is better to pass VA of the SoC
registers defined in MV_BASE and PA consistent with the value
in the Device Tree.
Approved by: cognet (mentor)
---
sys/arm/arm/locore.S | 4 ----
sys/arm/arm/mp_machdep.c | 8 ++++++--
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/sys/arm/arm/locore.S b/sys/arm/arm/locore.S
index ecd7f53..678f3bf 100644
--- a/sys/arm/arm/locore.S
+++ b/sys/arm/arm/locore.S
@@ -266,10 +266,6 @@ mmu_init_table:
/* map VA 0xc0000000..0xc3ffffff to PA */
MMU_INIT(KERNBASE, PHYSADDR, 64, L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_AP(AP_KRW))
MMU_INIT(0x48000000, 0x48000000, 1, L1_TYPE_S|L1_SHARED|L1_S_C|L1_S_AP(AP_KRW))
-#if defined(CPU_MV_PJ4B)
- /* map VA 0xf1000000..0xf1100000 to PA 0xd0000000 */
- MMU_INIT(0xf1000000, 0xd0000000, 1, L1_TYPE_S|L1_SHARED|L1_S_B|L1_S_AP(AP_KRW))
-#endif /* CPU_MV_PJ4B */
#endif /* SMP */
.word 0 /* end of table */
#endif
diff --git a/sys/arm/arm/mp_machdep.c b/sys/arm/arm/mp_machdep.c
index 2e5e1d3..c62e311 100644
--- a/sys/arm/arm/mp_machdep.c
+++ b/sys/arm/arm/mp_machdep.c
@@ -52,6 +52,10 @@ __FBSDID("$FreeBSD$");
#ifdef VFP
#include <machine/vfp.h>
#endif
+#ifdef CPU_MV_PJ4B
+#include <arm/mv/mvwin.h>
+#include <dev/fdt/fdt_common.h>
+#endif
#include "opt_smp.h"
@@ -131,8 +135,8 @@ cpu_mp_start(void)
#if defined(CPU_MV_PJ4B)
/* Add ARMADAXP registers required for snoop filter initialization */
- ((int *)(temp_pagetable_va))[0xf1000000 >> L1_S_SHIFT] =
- L1_TYPE_S|L1_SHARED|L1_S_B|L1_S_AP(AP_KRW)|0xd0000000;
+ ((int *)(temp_pagetable_va))[MV_BASE >> L1_S_SHIFT] =
+ L1_TYPE_S|L1_SHARED|L1_S_B|L1_S_AP(AP_KRW)|fdt_immr_pa;
#endif
temp_pagetable = (void*)(vtophys(temp_pagetable_va));
--
1.8.4
[-- Attachment #3 --]
From 32b53c8d70a326b73915a87bebc4d254c43bbf71 Mon Sep 17 00:00:00 2001
From: Zbigniew Bodek <zbb@semihalf.com>
Date: Tue, 22 Oct 2013 00:49:00 +0200
Subject: [PATCH 5/8] Fix-up DTB for Armada XP registers' base according to the
actual settings
Depending on u-boot's flavor some boards have their SoC registers
base address configured to 0xD0000000 and other to 0xF1000000.
U-boot is passing currently set value via CP15 register.
In order to create proper mapping for SoC registers and allow further
successful initialization it is necessary to replace fdt_immr_pa with
the real value and eventually fix-up device tree blob.
Approved by: cognet (mentor)
---
sys/arm/mv/common.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++++
sys/arm/mv/mv_machdep.c | 13 +++++++++
2 files changed, 83 insertions(+)
diff --git a/sys/arm/mv/common.c b/sys/arm/mv/common.c
index 2fafc65..44c22cb 100644
--- a/sys/arm/mv/common.c
+++ b/sys/arm/mv/common.c
@@ -2091,9 +2091,79 @@ fdt_fixup_busfreq(phandle_t root)
OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq));
}
+static void
+fdt_fixup_ranges(phandle_t root)
+{
+ phandle_t node;
+ pcell_t par_addr_cells, addr_cells, size_cells;
+ pcell_t ranges[3], reg[2], *rangesptr;
+ int len, tuple_size, tuples_count;
+ uint32_t base;
+
+ /* Fix-up SoC ranges according to real fdt_immr_pa */
+ if ((node = fdt_find_compatible(root, "simple-bus", 1)) != 0) {
+ if (fdt_addrsize_cells(node, &addr_cells, &size_cells) == 0 &&
+ (par_addr_cells = fdt_parent_addr_cells(node) <= 2)) {
+ tuple_size = sizeof(pcell_t) * (par_addr_cells +
+ addr_cells + size_cells);
+ len = OF_getprop(node, "ranges", ranges,
+ sizeof(ranges));
+ tuples_count = len / tuple_size;
+ /* Unexpected settings are not supported */
+ if (tuples_count != 1)
+ goto fixup_failed;
+
+ rangesptr = &ranges[0];
+ rangesptr += par_addr_cells;
+ base = fdt_data_get((void *)rangesptr, addr_cells);
+ *rangesptr = cpu_to_fdt32(fdt_immr_pa);
+ if (OF_setprop(node, "ranges", (void *)&ranges[0],
+ sizeof(ranges)) < 0)
+ goto fixup_failed;
+ }
+ }
+
+ /* Fix-up PCIe reg according to real PCIe registers' PA */
+ if ((node = fdt_find_compatible(root, "mrvl,pcie", 1)) != 0) {
+ if (fdt_addrsize_cells(OF_parent(node), &par_addr_cells,
+ &size_cells) == 0) {
+ tuple_size = sizeof(pcell_t) * (par_addr_cells +
+ size_cells);
+ len = OF_getprop(node, "reg", reg, sizeof(reg));
+ tuples_count = len / tuple_size;
+ /* Unexpected settings are not supported */
+ if (tuples_count != 1)
+ goto fixup_failed;
+
+ base = fdt_data_get((void *)®[0], par_addr_cells);
+ base &= ~0xFF000000;
+ base |= fdt_immr_pa;
+ reg[0] = cpu_to_fdt32(base);
+ if (OF_setprop(node, "reg", (void *)®[0],
+ sizeof(reg)) < 0)
+ goto fixup_failed;
+ }
+ }
+ /* Fix-up succeeded. May return and continue */
+ return;
+
+fixup_failed:
+ while (1) {
+ /*
+ * In case of any error while fixing ranges just hang.
+ * 1. No message can be displayed yet since console
+ * is not initialized.
+ * 2. Going further will cause failure on bus_space_map()
+ * relying on the wrong ranges or data abort when
+ * accessing PCIe registers.
+ */
+ }
+}
+
struct fdt_fixup_entry fdt_fixup_table[] = {
{ "mrvl,DB-88F6281", &fdt_fixup_busfreq },
{ "mrvl,DB-78460", &fdt_fixup_busfreq },
+ { "mrvl,DB-78460", &fdt_fixup_ranges },
{ NULL, NULL }
};
diff --git a/sys/arm/mv/mv_machdep.c b/sys/arm/mv/mv_machdep.c
index 58d183e..bdf3027 100644
--- a/sys/arm/mv/mv_machdep.c
+++ b/sys/arm/mv/mv_machdep.c
@@ -326,6 +326,19 @@ platform_devmap_init(void)
i = 0;
pmap_devmap_bootstrap_table = &fdt_devmap[0];
+#ifdef SOC_MV_ARMADAXP
+ vm_paddr_t cur_immr_pa;
+
+ /*
+ * Acquire SoC registers' base passed by u-boot and fill devmap
+ * accordingly. DTB is going to be modified basing on this data
+ * later.
+ */
+ __asm __volatile("mrc p15, 4, %0, c15, c0, 0" : "=r" (cur_immr_pa));
+ cur_immr_pa = (cur_immr_pa << 13) & 0xff000000;
+ if (cur_immr_pa != 0)
+ fdt_immr_pa = cur_immr_pa;
+#endif
/*
* IMMR range.
*/
--
1.8.4
[-- Attachment #4 --]
From 10c72e07fb4b2810d8c13509b90ef93425a3798e Mon Sep 17 00:00:00 2001
From: Zbigniew Bodek <zbb@semihalf.com>
Date: Tue, 22 Oct 2013 01:06:52 +0200
Subject: [PATCH 6/8] Change Armada XP kernel load address to the u-boot's end
address
Loading kernel to 0xf00000 has no practical reason.
Starting it from the u-boot's highest possible end address
(2MB counting from 0x0) makes more sense.
Approved by: cognet (mentor)
---
sys/arm/mv/armadaxp/std.armadaxp | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/sys/arm/mv/armadaxp/std.armadaxp b/sys/arm/mv/armadaxp/std.armadaxp
index bf2a5f6..d731ad3 100644
--- a/sys/arm/mv/armadaxp/std.armadaxp
+++ b/sys/arm/mv/armadaxp/std.armadaxp
@@ -1,16 +1,16 @@
# $FreeBSD$
-# kernel gets loaded at 0x00f00000 by the loader, but runs at virtual address
-# 0xc0f00000. RAM starts at 0. We put the pagetable at a reasonable place
+# kernel gets loaded at 0x00200000 by the loader, but runs at virtual address
+# 0xc0200000. RAM starts at 0. We put the pagetable at a reasonable place
# in memory, but may need to bounce it higher if there's a problem with this.
# We could paper over this by loading the kernel at 0xc0000000 virtual, but
# that leads to other complications, so we'll just reclaim the lower region of
# ram after we're loaded. Put the page tables for startup at 1MB.
-makeoptions KERNPHYSADDR=0x00f00000
-makeoptions KERNVIRTADDR=0xc0f00000
+makeoptions KERNPHYSADDR=0x00200000
+makeoptions KERNVIRTADDR=0xc0200000
-options KERNPHYSADDR=0x00f00000
-options KERNVIRTADDR=0xc0f00000
+options KERNPHYSADDR=0x00200000
+options KERNVIRTADDR=0xc0200000
options PHYSADDR=0x00000000
options STARTUP_PAGETABLE_ADDR=0x00100000
--
1.8.4
[-- Attachment #5 --]
From 9c8a1dd77805b3b4bce7839105019e9b88320ea8 Mon Sep 17 00:00:00 2001
From: Zbigniew Bodek <zbb@semihalf.com>
Date: Tue, 22 Oct 2013 01:52:49 +0200
Subject: [PATCH 7/8] Remove not working and deprecated PJ4Bv6 support
Sheeva PJ4Bv6 - based chips were only prototypes for V7 class Armada
SoC family. Current in-tree support for PJ4Bv6 will not work and also
there should be no platforms in active use that would incorporate that
CPU revision.
Approved by: cognet (mentor)
---
sys/arm/arm/cpufunc.c | 114 +----------------------------------
sys/arm/arm/cpufunc_asm_pj4b.S | 132 -----------------------------------------
sys/arm/arm/identcpu.c | 8 ---
sys/arm/include/armreg.h | 4 --
sys/arm/include/cpufunc.h | 9 ---
5 files changed, 2 insertions(+), 265 deletions(-)
diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c
index 8286188..c2e85e8 100644
--- a/sys/arm/arm/cpufunc.c
+++ b/sys/arm/arm/cpufunc.c
@@ -541,65 +541,6 @@ struct cpu_functions pj4bv7_cpufuncs = {
pj4bv7_setup /* cpu setup */
};
-
-struct cpu_functions pj4bv6_cpufuncs = {
- /* CPU functions */
-
- cpufunc_id, /* id */
- arm11_drain_writebuf, /* cpwait */
-
- /* MMU functions */
-
- cpufunc_control, /* control */
- cpufunc_domains, /* Domain */
- pj4b_setttb, /* Setttb */
- cpufunc_faultstatus, /* Faultstatus */
- cpufunc_faultaddress, /* Faultaddress */
-
- /* TLB functions */
-
- arm11_tlb_flushID, /* tlb_flushID */
- arm11_tlb_flushID_SE, /* tlb_flushID_SE */
- arm11_tlb_flushI, /* tlb_flushI */
- arm11_tlb_flushI_SE, /* tlb_flushI_SE */
- arm11_tlb_flushD, /* tlb_flushD */
- arm11_tlb_flushD_SE, /* tlb_flushD_SE */
-
- /* Cache operations */
- armv6_icache_sync_all, /* icache_sync_all */
- pj4b_icache_sync_range, /* icache_sync_range */
-
- armv6_dcache_wbinv_all, /* dcache_wbinv_all */
- pj4b_dcache_wbinv_range, /* dcache_wbinv_range */
- pj4b_dcache_inv_range, /* dcache_inv_range */
- pj4b_dcache_wb_range, /* dcache_wb_range */
-
- armv6_idcache_wbinv_all, /* idcache_wbinv_all */
- pj4b_idcache_wbinv_range, /* idcache_wbinv_all */
-
- (void *)cpufunc_nullop, /* l2cache_wbinv_all */
- (void *)cpufunc_nullop, /* l2cache_wbinv_range */
- (void *)cpufunc_nullop, /* l2cache_inv_range */
- (void *)cpufunc_nullop, /* l2cache_wb_range */
-
- /* Other functions */
-
- pj4b_drain_readbuf, /* flush_prefetchbuf */
- arm11_drain_writebuf, /* drain_writebuf */
- pj4b_flush_brnchtgt_all, /* flush_brnchtgt_C */
- pj4b_flush_brnchtgt_va, /* flush_brnchtgt_E */
-
- (void *)cpufunc_nullop, /* sleep */
-
- /* Soft functions */
-
- cpufunc_null_fixup, /* dataabt_fixup */
- cpufunc_null_fixup, /* prefetchabt_fixup */
-
- arm11_context_switch, /* context_switch */
-
- pj4bv6_setup /* cpu setup */
-};
#endif /* CPU_MV_PJ4B */
#ifdef CPU_SA110
@@ -1497,27 +1438,14 @@ set_cpufuncs()
#endif /* CPU_CORTEXA */
#if defined(CPU_MV_PJ4B)
- if (cputype == CPU_ID_MV88SV581X_V6 ||
- cputype == CPU_ID_MV88SV581X_V7 ||
+ if (cputype == CPU_ID_MV88SV581X_V7 ||
cputype == CPU_ID_MV88SV584X_V7 ||
- cputype == CPU_ID_ARM_88SV581X_V6 ||
cputype == CPU_ID_ARM_88SV581X_V7) {
- if (cpu_pfr(0) & ARM_PFR0_THUMBEE_MASK)
- cpufuncs = pj4bv7_cpufuncs;
- else
- cpufuncs = pj4bv6_cpufuncs;
-
- get_cachetype_cp15();
- pmap_pte_init_mmu_v6();
- goto out;
- } else if (cputype == CPU_ID_ARM_88SV584X_V6 ||
- cputype == CPU_ID_MV88SV584X_V6) {
- cpufuncs = pj4bv6_cpufuncs;
+ cpufuncs = pj4bv7_cpufuncs;
get_cachetype_cp15();
pmap_pte_init_mmu_v6();
goto out;
}
-
#endif /* CPU_MV_PJ4B */
#ifdef CPU_SA110
if (cputype == CPU_ID_SA110) {
@@ -2447,44 +2375,6 @@ arm11x6_setup(char *args)
#ifdef CPU_MV_PJ4B
void
-pj4bv6_setup(char *args)
-{
- int cpuctrl;
-
- pj4b_config();
-
- cpuctrl = CPU_CONTROL_MMU_ENABLE;
-#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
- cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
-#endif
- cpuctrl |= CPU_CONTROL_DC_ENABLE;
- cpuctrl |= (0xf << 3);
-#ifdef __ARMEB__
- cpuctrl |= CPU_CONTROL_BEND_ENABLE;
-#endif
- cpuctrl |= CPU_CONTROL_SYST_ENABLE;
- cpuctrl |= CPU_CONTROL_BPRD_ENABLE;
- cpuctrl |= CPU_CONTROL_IC_ENABLE;
- if (vector_page == ARM_VECTORS_HIGH)
- cpuctrl |= CPU_CONTROL_VECRELOC;
- cpuctrl |= (0x5 << 16);
- cpuctrl |= CPU_CONTROL_V6_EXTPAGE;
- /* XXX not yet */
- /* cpuctrl |= CPU_CONTROL_L2_ENABLE; */
-
- /* Make sure caches are clean. */
- cpu_idcache_wbinv_all();
- cpu_l2cache_wbinv_all();
-
- /* Set the control register */
- ctrl = cpuctrl;
- cpu_control(0xffffffff, cpuctrl);
-
- cpu_idcache_wbinv_all();
- cpu_l2cache_wbinv_all();
-}
-
-void
pj4bv7_setup(args)
char *args;
{
diff --git a/sys/arm/arm/cpufunc_asm_pj4b.S b/sys/arm/arm/cpufunc_asm_pj4b.S
index e6182fb..d8d400c 100644
--- a/sys/arm/arm/cpufunc_asm_pj4b.S
+++ b/sys/arm/arm/cpufunc_asm_pj4b.S
@@ -34,9 +34,6 @@ __FBSDID("$FreeBSD$");
#include <machine/param.h>
-.Lpj4b_cache_line_size:
- .word _C_LABEL(arm_pdcache_line_size)
-
.Lpj4b_sf_ctrl_reg:
.word 0xf1021820
@@ -52,135 +49,6 @@ ENTRY(pj4b_setttb)
RET
END(pj4b_setttb)
-ENTRY_NP(armv6_icache_sync_all)
- /*
- * We assume that the code here can never be out of sync with the
- * dcache, so that we can safely flush the Icache and fall through
- * into the Dcache cleaning code.
- */
- mov r0, #0
- mcr p15, 0, r0, c7, c5, 0 /* Invalidate ICache */
- mcr p15, 0, r0, c7, c10, 0 /* Clean (don't invalidate) DCache */
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
- RET
-END(armv6_icache_sync_all)
-
-ENTRY(pj4b_icache_sync_range)
- sub r1, r1, #1
- add r1, r0, r1
- mcrr p15, 0, r1, r0, c5 /* invalidate IC range */
- mcrr p15, 0, r1, r0, c12 /* clean DC range */
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
- RET
-END(pj4b_icache_sync_range)
-
-ENTRY(pj4b_dcache_inv_range)
- ldr ip, .Lpj4b_cache_line_size
- ldr ip, [ip]
- sub r1, r1, #1 /* Don't overrun */
- sub r3, ip, #1
- and r2, r0, r3
- add r1, r1, r2
- bic r0, r0, r3
-
- mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4413 */
-1:
- mcr p15, 0, r0, c7, c6, 1
- add r0, r0, ip
- subs r1, r1, ip
- bpl 1b
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
- RET
-END(pj4b_dcache_inv_range)
-
-ENTRY(armv6_idcache_wbinv_all)
- mov r0, #0
- mcr p15, 0, r0, c7, c5, 0 /* invalidate ICache */
- mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate DCache */
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
- RET
-END(armv6_idcache_wbinv_all)
-
-ENTRY(armv6_dcache_wbinv_all)
- mov r0, #0
- mcr p15, 0, r0, c7, c14, 0 /* clean and invalidate DCache */
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
- RET
-END(armv6_dcache_wbinv_all)
-
-ENTRY(pj4b_idcache_wbinv_range)
- ldr ip, .Lpj4b_cache_line_size
- ldr ip, [ip]
- sub r1, r1, #1 /* Don't overrun */
- sub r3, ip, #1
- and r2, r0, r3
- add r1, r1, r2
- bic r0, r0, r3
-
- mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */
-1:
-#ifdef SMP
- /* Request for ownership */
- ldr r2, [r0]
- str r2, [r0]
-#endif
- mcr p15, 0, r0, c7, c5, 1
- mcr p15, 0, r0, c7, c14, 1 /* L2C clean and invalidate entry */
- add r0, r0, ip
- subs r1, r1, ip
- bpl 1b
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
- RET
-END(pj4b_idcache_wbinv_range)
-
-ENTRY(pj4b_dcache_wbinv_range)
- ldr ip, .Lpj4b_cache_line_size
- ldr ip, [ip]
- sub r1, r1, #1 /* Don't overrun */
- sub r3, ip, #1
- and r2, r0, r3
- add r1, r1, r2
- bic r0, r0, r3
-
- mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */
-1:
-#ifdef SMP
- /* Request for ownership */
- ldr r2, [r0]
- str r2, [r0]
-#endif
- mcr p15, 0, r0, c7, c14, 1
- add r0, r0, ip
- subs r1, r1, ip
- bpl 1b
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
- RET
-END(pj4b_dcache_wbinv_range)
-
-ENTRY(pj4b_dcache_wb_range)
- ldr ip, .Lpj4b_cache_line_size
- ldr ip, [ip]
- sub r1, r1, #1 /* Don't overrun */
- sub r3, ip, #1
- and r2, r0, r3
- add r1, r1, r2
- bic r0, r0, r3
-
- mcr p15, 0, r0, c7, c10, 5 /* Data Memory Barrier err:4611 */
-1:
-#ifdef SMP
- /* Request for ownership */
- ldr r2, [r0]
- str r2, [r0]
-#endif
- mcr p15, 0, r0, c7, c10, 1 /* L2C clean single entry by MVA */
- add r0, r0, ip
- subs r1, r1, ip
- bpl 1b
- mcr p15, 0, r0, c7, c10, 4 /* drain the write buffer */
- RET
-END(pj4b_dcache_wb_range)
-
ENTRY(pj4b_drain_readbuf)
mcr p15, 0, r0, c7, c5, 4 /* flush prefetch buffers */
RET
diff --git a/sys/arm/arm/identcpu.c b/sys/arm/arm/identcpu.c
index 0bcf86e..219d49c 100644
--- a/sys/arm/arm/identcpu.c
+++ b/sys/arm/arm/identcpu.c
@@ -323,18 +323,10 @@ const struct cpuidtab cpuids[] = {
{ CPU_ID_MV88FR571_VD, CPU_CLASS_MARVELL, "Feroceon 88FR571-VD",
generic_steppings },
- { CPU_ID_MV88SV581X_V6, CPU_CLASS_MARVELL, "Sheeva 88SV581x",
- generic_steppings },
- { CPU_ID_ARM_88SV581X_V6, CPU_CLASS_MARVELL, "Sheeva 88SV581x",
- generic_steppings },
{ CPU_ID_MV88SV581X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV581x",
generic_steppings },
{ CPU_ID_ARM_88SV581X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV581x",
generic_steppings },
- { CPU_ID_MV88SV584X_V6, CPU_CLASS_MARVELL, "Sheeva 88SV584x",
- generic_steppings },
- { CPU_ID_ARM_88SV584X_V6, CPU_CLASS_MARVELL, "Sheeva 88SV584x",
- generic_steppings },
{ CPU_ID_MV88SV584X_V7, CPU_CLASS_MARVELL, "Sheeva 88SV584x",
generic_steppings },
diff --git a/sys/arm/include/armreg.h b/sys/arm/include/armreg.h
index bba4256..a07c2f8 100644
--- a/sys/arm/include/armreg.h
+++ b/sys/arm/include/armreg.h
@@ -173,14 +173,10 @@
#define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */
#endif
-#define CPU_ID_MV88SV581X_V6 0x560F5810 /* Marvell Sheeva 88SV581x v6 Core */
#define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */
-#define CPU_ID_MV88SV584X_V6 0x561F5840 /* Marvell Sheeva 88SV584x v6 Core */
#define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */
/* Marvell's CPUIDs with ARM ID in implementor field */
-#define CPU_ID_ARM_88SV581X_V6 0x410fb760 /* Marvell Sheeva 88SV581x v6 Core */
#define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */
-#define CPU_ID_ARM_88SV584X_V6 0x410FB020 /* Marvell Sheeva 88SV584x v6 Core */
#define CPU_ID_FA526 0x66015260
#define CPU_ID_FA626TE 0x66056260
diff --git a/sys/arm/include/cpufunc.h b/sys/arm/include/cpufunc.h
index 07c8258..6ba96c5 100644
--- a/sys/arm/include/cpufunc.h
+++ b/sys/arm/include/cpufunc.h
@@ -482,14 +482,6 @@ void arm11_drain_writebuf (void);
void pj4b_setttb (u_int);
-void pj4b_icache_sync_range (vm_offset_t, vm_size_t);
-
-void pj4b_dcache_wbinv_range (vm_offset_t, vm_size_t);
-void pj4b_dcache_inv_range (vm_offset_t, vm_size_t);
-void pj4b_dcache_wb_range (vm_offset_t, vm_size_t);
-
-void pj4b_idcache_wbinv_range (vm_offset_t, vm_size_t);
-
void pj4b_drain_readbuf (void);
void pj4b_flush_brnchtgt_all (void);
void pj4b_flush_brnchtgt_va (u_int);
@@ -523,7 +515,6 @@ void armv7_drain_writebuf (void);
void armv7_sev (void);
u_int armv7_auxctrl (u_int, u_int);
void pj4bv7_setup (char *string);
-void pj4bv6_setup (char *string);
void pj4b_config (void);
int get_core_id (void);
--
1.8.4
[-- Attachment #6 --]
From cce869b59d82d5076ae0600fd9da4f42cdf6c239 Mon Sep 17 00:00:00 2001
From: Zbigniew Bodek <zbb@semihalf.com>
Date: Tue, 22 Oct 2013 02:41:37 +0200
Subject: [PATCH 8/8] Switch off explicit broadcasting of the TLB flush
operations for PJ4B CPU
Since CPU_MV_PJ4B describes ARMv7 compliant CPU there is no need for
sending an IPI each time when TLB is flushed in any way.
Approved by: cognet (mentor)
---
sys/arm/include/cpufunc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sys/arm/include/cpufunc.h b/sys/arm/include/cpufunc.h
index 6ba96c5..d3e9ebe 100644
--- a/sys/arm/include/cpufunc.h
+++ b/sys/arm/include/cpufunc.h
@@ -188,7 +188,7 @@ extern u_int cputype;
#else
void tlb_broadcast(int);
-#ifdef CPU_CORTEXA
+#if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B)
#define TLB_BROADCAST /* No need to explicitely send an IPI */
#else
#define TLB_BROADCAST tlb_broadcast(7)
--
1.8.4
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